From 443a93905d71c135d0bf4783e61a0d181c60a62a Mon Sep 17 00:00:00 2001 From: lkcl Date: Sat, 9 Jan 2021 23:19:15 +0000 Subject: [PATCH] --- openpower/sv/ldst.mdwn | 1 + 1 file changed, 1 insertion(+) diff --git a/openpower/sv/ldst.mdwn b/openpower/sv/ldst.mdwn index 240962b5a..e019d9e9b 100644 --- a/openpower/sv/ldst.mdwn +++ b/openpower/sv/ldst.mdwn @@ -168,6 +168,7 @@ A summary of the effect of Vectorisation of src or dest: RA,RB RT.s RA/RB.s not vectorised Note that cache-inhibited LD/ST (`ldcix`) when VSPLAT is activated will perform **multiple** LD/ST operations, sequentially. `ldcix` even with scalar src will read the same memory location *multiple times*, storing the result in successive Vector destination registers. This because the cache-inhibit instructions are used to read and write memory-mapped peripherals. +If a genuine VSPLAT is required then a scalar cache-inhibited LD should be performed, followed by a VSPLAT-augmented mv. # LOAD/STORE Elwidths -- 2.30.2