From 44716655e6e62ebb09941a763e774148e151574f Mon Sep 17 00:00:00 2001 From: =?utf8?q?Marek=20Ol=C5=A1=C3=A1k?= Date: Sat, 19 Aug 2017 20:24:34 +0200 Subject: [PATCH] gallium: remove TGSI opcodes PUSHA, POPA, SAD, TXQ_LZ Reviewed-by: Roland Scheidegger --- src/gallium/auxiliary/gallivm/lp_bld_tgsi.c | 3 -- .../auxiliary/gallivm/lp_bld_tgsi_aos.c | 17 ------- src/gallium/auxiliary/nir/tgsi_to_nir.c | 6 --- src/gallium/auxiliary/tgsi/tgsi_exec.c | 12 ----- src/gallium/auxiliary/tgsi/tgsi_info.c | 11 ++-- src/gallium/auxiliary/tgsi/tgsi_opcode_tmp.h | 3 -- src/gallium/auxiliary/tgsi/tgsi_scan.c | 2 - src/gallium/auxiliary/tgsi/tgsi_util.c | 1 - src/gallium/docs/source/tgsi.rst | 50 ------------------- .../nouveau/codegen/nv50_ir_from_tgsi.cpp | 3 -- src/gallium/drivers/r300/r300_tgsi_to_rc.c | 1 - src/gallium/drivers/r600/r600_shader.c | 35 ++++++------- src/gallium/include/pipe/p_shader_tokens.h | 8 ++- 13 files changed, 23 insertions(+), 129 deletions(-) diff --git a/src/gallium/auxiliary/gallivm/lp_bld_tgsi.c b/src/gallium/auxiliary/gallivm/lp_bld_tgsi.c index 69863ab93c9..ebd4fe5f6a9 100644 --- a/src/gallium/auxiliary/gallivm/lp_bld_tgsi.c +++ b/src/gallium/auxiliary/gallivm/lp_bld_tgsi.c @@ -251,9 +251,6 @@ lp_build_tgsi_inst_llvm( case TGSI_OPCODE_UP2US: case TGSI_OPCODE_UP4B: case TGSI_OPCODE_UP4UB: - case TGSI_OPCODE_PUSHA: - case TGSI_OPCODE_POPA: - case TGSI_OPCODE_SAD: /* deprecated? */ assert(0); return FALSE; diff --git a/src/gallium/auxiliary/gallivm/lp_bld_tgsi_aos.c b/src/gallium/auxiliary/gallivm/lp_bld_tgsi_aos.c index 58c39facfe0..92ecb43a2b0 100644 --- a/src/gallium/auxiliary/gallivm/lp_bld_tgsi_aos.c +++ b/src/gallium/auxiliary/gallivm/lp_bld_tgsi_aos.c @@ -776,18 +776,6 @@ lp_emit_instruction_aos( case TGSI_OPCODE_ENDSUB: return FALSE; - case TGSI_OPCODE_PUSHA: - /* deprecated? */ - assert(0); - return FALSE; - break; - - case TGSI_OPCODE_POPA: - /* deprecated? */ - assert(0); - return FALSE; - break; - case TGSI_OPCODE_CEIL: src0 = lp_build_emit_fetch(&bld->bld_base, inst, 0, LP_CHAN_ALL); dst0 = lp_build_ceil(&bld->bld_base.base, src0); @@ -838,11 +826,6 @@ lp_emit_instruction_aos( return FALSE; break; - case TGSI_OPCODE_SAD: - assert(0); - return FALSE; - break; - case TGSI_OPCODE_TXF: assert(0); return FALSE; diff --git a/src/gallium/auxiliary/nir/tgsi_to_nir.c b/src/gallium/auxiliary/nir/tgsi_to_nir.c index d4914acb7d7..703013b7222 100644 --- a/src/gallium/auxiliary/nir/tgsi_to_nir.c +++ b/src/gallium/auxiliary/nir/tgsi_to_nir.c @@ -1588,9 +1588,6 @@ static const nir_op op_trans[TGSI_OPCODE_LAST] = { [TGSI_OPCODE_DDX_FINE] = nir_op_fddx_fine, [TGSI_OPCODE_DDY_FINE] = nir_op_fddy_fine, - [TGSI_OPCODE_PUSHA] = 0, /* XXX */ - [TGSI_OPCODE_POPA] = 0, /* XXX */ - [TGSI_OPCODE_CEIL] = nir_op_fceil, [TGSI_OPCODE_I2F] = nir_op_i2f32, [TGSI_OPCODE_NOT] = nir_op_inot, @@ -1600,7 +1597,6 @@ static const nir_op op_trans[TGSI_OPCODE_LAST] = { [TGSI_OPCODE_OR] = nir_op_ior, [TGSI_OPCODE_MOD] = nir_op_umod, [TGSI_OPCODE_XOR] = nir_op_ixor, - [TGSI_OPCODE_SAD] = 0, /* XXX */ [TGSI_OPCODE_TXF] = 0, [TGSI_OPCODE_TXQ] = 0, @@ -1614,7 +1610,6 @@ static const nir_op op_trans[TGSI_OPCODE_LAST] = { [TGSI_OPCODE_ENDLOOP] = 0, [TGSI_OPCODE_ENDSUB] = 0, /* XXX: no function calls */ - [TGSI_OPCODE_TXQ_LZ] = 0, [TGSI_OPCODE_NOP] = 0, [TGSI_OPCODE_FSEQ] = nir_op_feq, [TGSI_OPCODE_FSGE] = nir_op_fge, @@ -1835,7 +1830,6 @@ ttn_emit_instruction(struct ttn_compile *c) case TGSI_OPCODE_TEX2: case TGSI_OPCODE_TXL2: case TGSI_OPCODE_TXB2: - case TGSI_OPCODE_TXQ_LZ: case TGSI_OPCODE_TXF: case TGSI_OPCODE_TG4: case TGSI_OPCODE_LODQ: diff --git a/src/gallium/auxiliary/tgsi/tgsi_exec.c b/src/gallium/auxiliary/tgsi/tgsi_exec.c index 97c75e999c5..cc3e232d388 100644 --- a/src/gallium/auxiliary/tgsi/tgsi_exec.c +++ b/src/gallium/auxiliary/tgsi/tgsi_exec.c @@ -5528,14 +5528,6 @@ exec_instruction( *pc = -1; break; - case TGSI_OPCODE_PUSHA: - assert (0); - break; - - case TGSI_OPCODE_POPA: - assert (0); - break; - case TGSI_OPCODE_CEIL: exec_vector_unary(mach, inst, micro_ceil, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT); break; @@ -5572,10 +5564,6 @@ exec_instruction( exec_vector_binary(mach, inst, micro_xor, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT); break; - case TGSI_OPCODE_SAD: - assert (0); - break; - case TGSI_OPCODE_TXF: exec_txf(mach, inst); break; diff --git a/src/gallium/auxiliary/tgsi/tgsi_info.c b/src/gallium/auxiliary/tgsi/tgsi_info.c index 30bad6d6f7a..38c4a81d03e 100644 --- a/src/gallium/auxiliary/tgsi/tgsi_info.c +++ b/src/gallium/auxiliary/tgsi/tgsi_info.c @@ -118,8 +118,8 @@ static const struct tgsi_opcode_info opcode_info[TGSI_OPCODE_LAST] = { 0, 0, 0, 0, 0, 1, 0, NONE, "ENDIF", TGSI_OPCODE_ENDIF }, { 1, 1, 0, 0, 0, 0, 0, COMP, "DDX_FINE", TGSI_OPCODE_DDX_FINE }, { 1, 1, 0, 0, 0, 0, 0, COMP, "DDY_FINE", TGSI_OPCODE_DDY_FINE }, - { 0, 1, 0, 0, 0, 0, 0, NONE, "PUSHA", TGSI_OPCODE_PUSHA }, - { 1, 0, 0, 0, 0, 0, 0, NONE, "POPA", TGSI_OPCODE_POPA }, + { 0, 1, 0, 0, 0, 0, 0, NONE, "", 81 }, /* removed */ + { 1, 0, 0, 0, 0, 0, 0, NONE, "", 82 }, /* removed */ { 1, 1, 0, 0, 0, 0, 0, COMP, "CEIL", TGSI_OPCODE_CEIL }, { 1, 1, 0, 0, 0, 0, 0, COMP, "I2F", TGSI_OPCODE_I2F }, { 1, 1, 0, 0, 0, 0, 0, COMP, "NOT", TGSI_OPCODE_NOT }, @@ -130,7 +130,7 @@ static const struct tgsi_opcode_info opcode_info[TGSI_OPCODE_LAST] = { 1, 2, 0, 0, 0, 0, 0, COMP, "OR", TGSI_OPCODE_OR }, { 1, 2, 0, 0, 0, 0, 0, COMP, "MOD", TGSI_OPCODE_MOD }, { 1, 2, 0, 0, 0, 0, 0, COMP, "XOR", TGSI_OPCODE_XOR }, - { 1, 3, 0, 0, 0, 0, 0, COMP, "SAD", TGSI_OPCODE_SAD }, + { 1, 3, 0, 0, 0, 0, 0, COMP, "", 93 }, /* removed */ { 1, 2, 1, 0, 0, 0, 0, OTHR, "TXF", TGSI_OPCODE_TXF }, { 1, 2, 1, 0, 0, 0, 0, OTHR, "TXQ", TGSI_OPCODE_TXQ }, { 0, 0, 0, 0, 0, 0, 0, NONE, "CONT", TGSI_OPCODE_CONT }, @@ -140,7 +140,7 @@ static const struct tgsi_opcode_info opcode_info[TGSI_OPCODE_LAST] = { 0, 0, 0, 0, 0, 0, 1, NONE, "BGNSUB", TGSI_OPCODE_BGNSUB }, { 0, 0, 0, 0, 1, 1, 0, NONE, "ENDLOOP", TGSI_OPCODE_ENDLOOP }, { 0, 0, 0, 0, 0, 1, 0, NONE, "ENDSUB", TGSI_OPCODE_ENDSUB }, - { 1, 1, 1, 0, 0, 0, 0, OTHR, "TXQ_LZ", TGSI_OPCODE_TXQ_LZ }, + { 1, 1, 1, 0, 0, 0, 0, OTHR, "", 103 }, /* removed */ { 1, 1, 1, 0, 0, 0, 0, OTHR, "TXQS", TGSI_OPCODE_TXQS }, { 1, 1, 0, 0, 0, 0, 0, OTHR, "RESQ", TGSI_OPCODE_RESQ }, { 1, 1, 0, 0, 0, 0, 0, COMP, "READ_FIRST", TGSI_OPCODE_READ_FIRST }, @@ -356,9 +356,7 @@ tgsi_opcode_infer_type( uint opcode ) case TGSI_OPCODE_AND: case TGSI_OPCODE_OR: case TGSI_OPCODE_XOR: - case TGSI_OPCODE_SAD: /* XXX some src args may be signed for SAD ? */ case TGSI_OPCODE_TXQ: - case TGSI_OPCODE_TXQ_LZ: case TGSI_OPCODE_TXQS: case TGSI_OPCODE_F2U: case TGSI_OPCODE_UDIV: @@ -499,7 +497,6 @@ tgsi_opcode_infer_src_type( uint opcode ) return TGSI_TYPE_SIGNED; case TGSI_OPCODE_ARL: case TGSI_OPCODE_ARR: - case TGSI_OPCODE_TXQ_LZ: case TGSI_OPCODE_F2D: case TGSI_OPCODE_F2I: case TGSI_OPCODE_F2U: diff --git a/src/gallium/auxiliary/tgsi/tgsi_opcode_tmp.h b/src/gallium/auxiliary/tgsi/tgsi_opcode_tmp.h index d11d0e545af..b5dcd4590d6 100644 --- a/src/gallium/auxiliary/tgsi/tgsi_opcode_tmp.h +++ b/src/gallium/auxiliary/tgsi/tgsi_opcode_tmp.h @@ -103,8 +103,6 @@ OP01_LBL(IF) OP01_LBL(UIF) OP00_LBL(ELSE) OP00(ENDIF) -OP01(PUSHA) -OP10(POPA) OP11(CEIL) OP11(I2F) OP11(NOT) @@ -114,7 +112,6 @@ OP12(AND) OP12(OR) OP12(MOD) OP12(XOR) -OP13(SAD) OP12_TEX(TXF) OP12_TEX(TXQ) OP00(CONT) diff --git a/src/gallium/auxiliary/tgsi/tgsi_scan.c b/src/gallium/auxiliary/tgsi/tgsi_scan.c index 6e51972e5d5..2fd7d7c0f9e 100644 --- a/src/gallium/auxiliary/tgsi/tgsi_scan.c +++ b/src/gallium/auxiliary/tgsi/tgsi_scan.c @@ -60,7 +60,6 @@ is_mem_query_inst(unsigned opcode) return opcode == TGSI_OPCODE_RESQ || opcode == TGSI_OPCODE_TXQ || opcode == TGSI_OPCODE_TXQS || - opcode == TGSI_OPCODE_TXQ_LZ || opcode == TGSI_OPCODE_LODQ; } @@ -92,7 +91,6 @@ computes_derivative(unsigned opcode) opcode != TGSI_OPCODE_TXL && opcode != TGSI_OPCODE_TXL2 && opcode != TGSI_OPCODE_TXQ && - opcode != TGSI_OPCODE_TXQ_LZ && opcode != TGSI_OPCODE_TXQS; } diff --git a/src/gallium/auxiliary/tgsi/tgsi_util.c b/src/gallium/auxiliary/tgsi/tgsi_util.c index f6d2d3f4c30..932545cb897 100644 --- a/src/gallium/auxiliary/tgsi/tgsi_util.c +++ b/src/gallium/auxiliary/tgsi/tgsi_util.c @@ -214,7 +214,6 @@ tgsi_util_get_inst_usage_mask(const struct tgsi_full_instruction *inst, case TGSI_OPCODE_AND: case TGSI_OPCODE_OR: case TGSI_OPCODE_XOR: - case TGSI_OPCODE_SAD: case TGSI_OPCODE_FSEQ: case TGSI_OPCODE_FSGE: case TGSI_OPCODE_FSLT: diff --git a/src/gallium/docs/source/tgsi.rst b/src/gallium/docs/source/tgsi.rst index d1e7c88905e..83ef7853949 100644 --- a/src/gallium/docs/source/tgsi.rst +++ b/src/gallium/docs/source/tgsi.rst @@ -835,37 +835,6 @@ This instruction replicates its result. dst = texture\_sample(unit, coord, lod) -.. opcode:: PUSHA - Push Address Register On Stack - - push(src.x) - push(src.y) - push(src.z) - push(src.w) - -.. note:: - - Considered for cleanup. - -.. note:: - - Considered for removal. - -.. opcode:: POPA - Pop Address Register From Stack - - dst.w = pop() - dst.z = pop() - dst.y = pop() - dst.x = pop() - -.. note:: - - Considered for cleanup. - -.. note:: - - Considered for removal. - - .. opcode:: CALLNZ - Subroutine Call If Not Zero TBD @@ -932,19 +901,6 @@ XXX doesn't look like most of the opcodes really belong here. destination register, which is assumed to be an address (ADDR) register. -.. opcode:: SAD - Sum Of Absolute Differences - -.. math:: - - dst.x = |src0.x - src1.x| + src2.x - - dst.y = |src0.y - src1.y| + src2.y - - dst.z = |src0.z - src1.z| + src2.z - - dst.w = |src0.w - src1.w| + src2.w - - .. opcode:: TXF - Texel Fetch As per NV_gpu_shader4, extract a single texel from a specified texture @@ -961,12 +917,6 @@ XXX doesn't look like most of the opcodes really belong here. TXF(uint_vec coord, int_vec offset). -.. opcode:: TXF_LZ - Texel Fetch - - This is the same as TXF with level = 0. Like TXF, it obeys - pipe_sampler_view::u.tex.first_level. - - .. opcode:: TXQ - Texture Size Query As per NV_gpu_program4, retrieve the dimensions of the texture depending on diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp index b98015a6389..0b1f5503348 100644 --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp @@ -620,7 +620,6 @@ nv50_ir::DataType Instruction::inferSrcType() const case TGSI_OPCODE_ISHR: case TGSI_OPCODE_ISLT: case TGSI_OPCODE_ISSG: - case TGSI_OPCODE_SAD: // not sure about SAD, but no one has a float version case TGSI_OPCODE_MOD: case TGSI_OPCODE_UARL: case TGSI_OPCODE_ATOMIMIN: @@ -845,7 +844,6 @@ static nv50_ir::operation translateOpcode(uint opcode) NV50_IR_OPCODE_CASE(OR, OR); NV50_IR_OPCODE_CASE(MOD, MOD); NV50_IR_OPCODE_CASE(XOR, XOR); - NV50_IR_OPCODE_CASE(SAD, SAD); NV50_IR_OPCODE_CASE(TXF, TXF); NV50_IR_OPCODE_CASE(TXF_LZ, TXF); NV50_IR_OPCODE_CASE(TXQ, TXQ); @@ -3198,7 +3196,6 @@ Converter::handleInstruction(const struct tgsi_full_instruction *insn) break; case TGSI_OPCODE_MAD: case TGSI_OPCODE_UMAD: - case TGSI_OPCODE_SAD: case TGSI_OPCODE_FMA: FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) { src0 = fetchSrc(0, c); diff --git a/src/gallium/drivers/r300/r300_tgsi_to_rc.c b/src/gallium/drivers/r300/r300_tgsi_to_rc.c index a9e3d6d7477..81cf72bced0 100644 --- a/src/gallium/drivers/r300/r300_tgsi_to_rc.c +++ b/src/gallium/drivers/r300/r300_tgsi_to_rc.c @@ -108,7 +108,6 @@ static unsigned translate_opcode(unsigned opcode) /* case TGSI_OPCODE_OR: return RC_OPCODE_OR; */ /* case TGSI_OPCODE_MOD: return RC_OPCODE_MOD; */ /* case TGSI_OPCODE_XOR: return RC_OPCODE_XOR; */ - /* case TGSI_OPCODE_SAD: return RC_OPCODE_SAD; */ /* case TGSI_OPCODE_TXF: return RC_OPCODE_TXF; */ /* case TGSI_OPCODE_TXQ: return RC_OPCODE_TXQ; */ case TGSI_OPCODE_CONT: return RC_OPCODE_CONT; diff --git a/src/gallium/drivers/r600/r600_shader.c b/src/gallium/drivers/r600/r600_shader.c index 8c5e6ff72d6..74f5add1191 100644 --- a/src/gallium/drivers/r600/r600_shader.c +++ b/src/gallium/drivers/r600/r600_shader.c @@ -6797,13 +6797,12 @@ static int tgsi_tex(struct r600_shader_ctx *ctx) /* Texture fetch instructions can only use gprs as source. * Also they cannot negate the source or take the absolute value */ - const boolean src_requires_loading = (inst->Instruction.Opcode != TGSI_OPCODE_TXQ_LZ && - inst->Instruction.Opcode != TGSI_OPCODE_TXQS && + const boolean src_requires_loading = (inst->Instruction.Opcode != TGSI_OPCODE_TXQS && tgsi_tex_src_requires_loading(ctx, 0)) || read_compressed_msaa || txf_add_offsets; boolean src_loaded = FALSE; - unsigned sampler_src_reg = inst->Instruction.Opcode == TGSI_OPCODE_TXQ_LZ ? 0 : 1; + unsigned sampler_src_reg = 1; int8_t offset_x = 0, offset_y = 0, offset_z = 0; boolean has_txq_cube_array_z = false; unsigned sampler_index_mode; @@ -6911,8 +6910,7 @@ static int tgsi_tex(struct r600_shader_ctx *ctx) inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY || inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE || inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) && - inst->Instruction.Opcode != TGSI_OPCODE_TXQ && - inst->Instruction.Opcode != TGSI_OPCODE_TXQ_LZ) { + inst->Instruction.Opcode != TGSI_OPCODE_TXQ) { static const unsigned src0_swizzle[] = {2, 2, 0, 1}; static const unsigned src1_swizzle[] = {1, 0, 2, 2}; @@ -7555,8 +7553,7 @@ static int tgsi_tex(struct r600_shader_ctx *ctx) } - if (inst->Instruction.Opcode == TGSI_OPCODE_TXQ_LZ || - inst->Instruction.Opcode == TGSI_OPCODE_TXQS) { + if (inst->Instruction.Opcode == TGSI_OPCODE_TXQS) { tex.src_sel_x = 4; tex.src_sel_y = 4; tex.src_sel_z = 4; @@ -9152,8 +9149,8 @@ static const struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[] [TGSI_OPCODE_ENDIF] = { ALU_OP0_NOP, tgsi_endif}, [TGSI_OPCODE_DDX_FINE] = { ALU_OP0_NOP, tgsi_unsupported}, [TGSI_OPCODE_DDY_FINE] = { ALU_OP0_NOP, tgsi_unsupported}, - [TGSI_OPCODE_PUSHA] = { ALU_OP0_NOP, tgsi_unsupported}, - [TGSI_OPCODE_POPA] = { ALU_OP0_NOP, tgsi_unsupported}, + [81] = { ALU_OP0_NOP, tgsi_unsupported}, + [82] = { ALU_OP0_NOP, tgsi_unsupported}, [TGSI_OPCODE_CEIL] = { ALU_OP1_CEIL, tgsi_op2}, [TGSI_OPCODE_I2F] = { ALU_OP1_INT_TO_FLT, tgsi_op2_trans}, [TGSI_OPCODE_NOT] = { ALU_OP1_NOT_INT, tgsi_op2}, @@ -9164,7 +9161,7 @@ static const struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[] [TGSI_OPCODE_OR] = { ALU_OP2_OR_INT, tgsi_op2}, [TGSI_OPCODE_MOD] = { ALU_OP0_NOP, tgsi_imod}, [TGSI_OPCODE_XOR] = { ALU_OP2_XOR_INT, tgsi_op2}, - [TGSI_OPCODE_SAD] = { ALU_OP0_NOP, tgsi_unsupported}, + [93] = { ALU_OP0_NOP, tgsi_unsupported}, [TGSI_OPCODE_TXF] = { FETCH_OP_LD, tgsi_tex}, [TGSI_OPCODE_TXQ] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex}, [TGSI_OPCODE_CONT] = { CF_OP_LOOP_CONTINUE, tgsi_loop_brk_cont}, @@ -9174,7 +9171,7 @@ static const struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[] [TGSI_OPCODE_BGNSUB] = { ALU_OP0_NOP, tgsi_unsupported}, [TGSI_OPCODE_ENDLOOP] = { ALU_OP0_NOP, tgsi_endloop}, [TGSI_OPCODE_ENDSUB] = { ALU_OP0_NOP, tgsi_unsupported}, - [TGSI_OPCODE_TXQ_LZ] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex}, + [103] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex}, [TGSI_OPCODE_TXQS] = { FETCH_OP_GET_NUMBER_OF_SAMPLES, tgsi_tex}, [TGSI_OPCODE_RESQ] = { ALU_OP0_NOP, tgsi_unsupported}, [106] = { ALU_OP0_NOP, tgsi_unsupported}, @@ -9350,8 +9347,8 @@ static const struct r600_shader_tgsi_instruction eg_shader_tgsi_instruction[] = [TGSI_OPCODE_ENDIF] = { ALU_OP0_NOP, tgsi_endif}, [TGSI_OPCODE_DDX_FINE] = { FETCH_OP_GET_GRADIENTS_H, tgsi_tex}, [TGSI_OPCODE_DDY_FINE] = { FETCH_OP_GET_GRADIENTS_V, tgsi_tex}, - [TGSI_OPCODE_PUSHA] = { ALU_OP0_NOP, tgsi_unsupported}, - [TGSI_OPCODE_POPA] = { ALU_OP0_NOP, tgsi_unsupported}, + [82] = { ALU_OP0_NOP, tgsi_unsupported}, + [83] = { ALU_OP0_NOP, tgsi_unsupported}, [TGSI_OPCODE_CEIL] = { ALU_OP1_CEIL, tgsi_op2}, [TGSI_OPCODE_I2F] = { ALU_OP1_INT_TO_FLT, tgsi_op2_trans}, [TGSI_OPCODE_NOT] = { ALU_OP1_NOT_INT, tgsi_op2}, @@ -9362,7 +9359,7 @@ static const struct r600_shader_tgsi_instruction eg_shader_tgsi_instruction[] = [TGSI_OPCODE_OR] = { ALU_OP2_OR_INT, tgsi_op2}, [TGSI_OPCODE_MOD] = { ALU_OP0_NOP, tgsi_imod}, [TGSI_OPCODE_XOR] = { ALU_OP2_XOR_INT, tgsi_op2}, - [TGSI_OPCODE_SAD] = { ALU_OP0_NOP, tgsi_unsupported}, + [93] = { ALU_OP0_NOP, tgsi_unsupported}, [TGSI_OPCODE_TXF] = { FETCH_OP_LD, tgsi_tex}, [TGSI_OPCODE_TXQ] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex}, [TGSI_OPCODE_CONT] = { CF_OP_LOOP_CONTINUE, tgsi_loop_brk_cont}, @@ -9372,7 +9369,7 @@ static const struct r600_shader_tgsi_instruction eg_shader_tgsi_instruction[] = [TGSI_OPCODE_BGNSUB] = { ALU_OP0_NOP, tgsi_unsupported}, [TGSI_OPCODE_ENDLOOP] = { ALU_OP0_NOP, tgsi_endloop}, [TGSI_OPCODE_ENDSUB] = { ALU_OP0_NOP, tgsi_unsupported}, - [TGSI_OPCODE_TXQ_LZ] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex}, + [103] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex}, [TGSI_OPCODE_TXQS] = { FETCH_OP_GET_NUMBER_OF_SAMPLES, tgsi_tex}, [TGSI_OPCODE_RESQ] = { ALU_OP0_NOP, tgsi_unsupported}, [106] = { ALU_OP0_NOP, tgsi_unsupported}, @@ -9573,8 +9570,8 @@ static const struct r600_shader_tgsi_instruction cm_shader_tgsi_instruction[] = [TGSI_OPCODE_ENDIF] = { ALU_OP0_NOP, tgsi_endif}, [TGSI_OPCODE_DDX_FINE] = { FETCH_OP_GET_GRADIENTS_H, tgsi_tex}, [TGSI_OPCODE_DDY_FINE] = { FETCH_OP_GET_GRADIENTS_V, tgsi_tex}, - [TGSI_OPCODE_PUSHA] = { ALU_OP0_NOP, tgsi_unsupported}, - [TGSI_OPCODE_POPA] = { ALU_OP0_NOP, tgsi_unsupported}, + [82] = { ALU_OP0_NOP, tgsi_unsupported}, + [83] = { ALU_OP0_NOP, tgsi_unsupported}, [TGSI_OPCODE_CEIL] = { ALU_OP1_CEIL, tgsi_op2}, [TGSI_OPCODE_I2F] = { ALU_OP1_INT_TO_FLT, tgsi_op2}, [TGSI_OPCODE_NOT] = { ALU_OP1_NOT_INT, tgsi_op2}, @@ -9585,7 +9582,7 @@ static const struct r600_shader_tgsi_instruction cm_shader_tgsi_instruction[] = [TGSI_OPCODE_OR] = { ALU_OP2_OR_INT, tgsi_op2}, [TGSI_OPCODE_MOD] = { ALU_OP0_NOP, tgsi_imod}, [TGSI_OPCODE_XOR] = { ALU_OP2_XOR_INT, tgsi_op2}, - [TGSI_OPCODE_SAD] = { ALU_OP0_NOP, tgsi_unsupported}, + [93] = { ALU_OP0_NOP, tgsi_unsupported}, [TGSI_OPCODE_TXF] = { FETCH_OP_LD, tgsi_tex}, [TGSI_OPCODE_TXQ] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex}, [TGSI_OPCODE_CONT] = { CF_OP_LOOP_CONTINUE, tgsi_loop_brk_cont}, @@ -9595,7 +9592,7 @@ static const struct r600_shader_tgsi_instruction cm_shader_tgsi_instruction[] = [TGSI_OPCODE_BGNSUB] = { ALU_OP0_NOP, tgsi_unsupported}, [TGSI_OPCODE_ENDLOOP] = { ALU_OP0_NOP, tgsi_endloop}, [TGSI_OPCODE_ENDSUB] = { ALU_OP0_NOP, tgsi_unsupported}, - [TGSI_OPCODE_TXQ_LZ] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex}, + [103] = { FETCH_OP_GET_TEXTURE_RESINFO, tgsi_tex}, [TGSI_OPCODE_TXQS] = { FETCH_OP_GET_NUMBER_OF_SAMPLES, tgsi_tex}, [TGSI_OPCODE_RESQ] = { ALU_OP0_NOP, tgsi_unsupported}, [106] = { ALU_OP0_NOP, tgsi_unsupported}, diff --git a/src/gallium/include/pipe/p_shader_tokens.h b/src/gallium/include/pipe/p_shader_tokens.h index aa0fb3e3b3e..502446dc858 100644 --- a/src/gallium/include/pipe/p_shader_tokens.h +++ b/src/gallium/include/pipe/p_shader_tokens.h @@ -419,9 +419,7 @@ struct tgsi_property_data { #define TGSI_OPCODE_DDX_FINE 79 #define TGSI_OPCODE_DDY_FINE 80 - -#define TGSI_OPCODE_PUSHA 81 -#define TGSI_OPCODE_POPA 82 +/* gap */ #define TGSI_OPCODE_CEIL 83 #define TGSI_OPCODE_I2F 84 #define TGSI_OPCODE_NOT 85 @@ -432,7 +430,7 @@ struct tgsi_property_data { #define TGSI_OPCODE_OR 90 #define TGSI_OPCODE_MOD 91 #define TGSI_OPCODE_XOR 92 -#define TGSI_OPCODE_SAD 93 +/* gap */ #define TGSI_OPCODE_TXF 94 #define TGSI_OPCODE_TXQ 95 #define TGSI_OPCODE_CONT 96 @@ -442,7 +440,7 @@ struct tgsi_property_data { #define TGSI_OPCODE_BGNSUB 100 #define TGSI_OPCODE_ENDLOOP 101 #define TGSI_OPCODE_ENDSUB 102 -#define TGSI_OPCODE_TXQ_LZ 103 /* TXQ for mipmap level 0 */ +/* gap */ #define TGSI_OPCODE_TXQS 104 #define TGSI_OPCODE_RESQ 105 #define TGSI_OPCODE_READ_FIRST 106 -- 2.30.2