From 44916c758cde1514ecebcc636081eb5c3219bbfe Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 13 May 2020 22:37:21 +0100 Subject: [PATCH] remove Logical operations from ALU pipeline --- src/soc/alu/formal/proof_main_stage.py | 6 ------ src/soc/alu/main_stage.py | 12 ------------ src/soc/alu/test/test_pipe_caller.py | 13 +------------ 3 files changed, 1 insertion(+), 30 deletions(-) diff --git a/src/soc/alu/formal/proof_main_stage.py b/src/soc/alu/formal/proof_main_stage.py index e25b1c51..f102fc2b 100644 --- a/src/soc/alu/formal/proof_main_stage.py +++ b/src/soc/alu/formal/proof_main_stage.py @@ -68,12 +68,6 @@ class Driver(Elaboratable): with m.Switch(rec.insn_type): with m.Case(InternalOp.OP_ADD): comb += Assert(Cat(o, carry_out) == (a + b + carry_in)) - with m.Case(InternalOp.OP_AND): - comb += Assert(dut.o.o == a & b) - with m.Case(InternalOp.OP_OR): - comb += Assert(dut.o.o == a | b) - with m.Case(InternalOp.OP_XOR): - comb += Assert(dut.o.o == a ^ b) return m diff --git a/src/soc/alu/main_stage.py b/src/soc/alu/main_stage.py index f5347d3f..a89c2333 100644 --- a/src/soc/alu/main_stage.py +++ b/src/soc/alu/main_stage.py @@ -50,18 +50,6 @@ class ALUMainStage(PipeModBase): comb += self.o.o.eq(add_output[1:-1]) comb += self.o.carry_out.eq(add_output[-1]) - #### and #### - with m.Case(InternalOp.OP_AND): - comb += self.o.o.eq(self.i.a & self.i.b) - - #### or #### - with m.Case(InternalOp.OP_OR): - comb += self.o.o.eq(self.i.a | self.i.b) - - #### xor #### - with m.Case(InternalOp.OP_XOR): - comb += self.o.o.eq(self.i.a ^ self.i.b) - #### exts (sign-extend) #### with m.Case(InternalOp.OP_EXTS): with m.If(self.i.ctx.op.data_len == 1): diff --git a/src/soc/alu/test/test_pipe_caller.py b/src/soc/alu/test/test_pipe_caller.py index 604b5af2..c7afb9a6 100644 --- a/src/soc/alu/test/test_pipe_caller.py +++ b/src/soc/alu/test/test_pipe_caller.py @@ -102,7 +102,7 @@ class ALUTestCase(FHDLTestCase): test_data.append(tc) def test_rand(self): - insns = ["add", "add.", "and", "or", "xor", "subf"] + insns = ["add", "add.", "subf"] for i in range(40): choice = random.choice(insns) lst = [f"{choice} 3, 1, 2"] @@ -122,17 +122,6 @@ class ALUTestCase(FHDLTestCase): initial_regs[1] = random.randint(0, (1<<64)-1) self.run_tst_program(Program(lst), initial_regs) - def test_rand_imm_logical(self): - insns = ["andi.", "andis.", "ori", "oris", "xori", "xoris"] - for i in range(10): - choice = random.choice(insns) - imm = random.randint(0, (1<<16)-1) - lst = [f"{choice} 3, 1, {imm}"] - print(lst) - initial_regs = [0] * 32 - initial_regs[1] = random.randint(0, (1<<64)-1) - self.run_tst_program(Program(lst), initial_regs) - def test_adde(self): lst = ["adde. 5, 6, 7"] initial_regs = [0] * 32 -- 2.30.2