From 44a48437706e09010d3b9b397730de1e45ce2638 Mon Sep 17 00:00:00 2001
From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 9 Feb 2020 18:41:03 +0000
Subject: [PATCH] boolean logic invert bool to all

---
 src/ieee754/fpdiv/mulAddRecFN.py | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/ieee754/fpdiv/mulAddRecFN.py b/src/ieee754/fpdiv/mulAddRecFN.py
index 5a36706f..ca85f3da 100644
--- a/src/ieee754/fpdiv/mulAddRecFN.py
+++ b/src/ieee754/fpdiv/mulAddRecFN.py
@@ -338,7 +338,7 @@ class mulAddRecFNToRaw_postMul(Elaboratable):
                     intermed_highAlignedSigC[(sigWidth + 1):sigWidth],
                     0b0))),
             CDom_absSigSumExtra.eq(Mux(doSubMags,
-                          (~sigSum[1:sigWidth+1]).bool(),
+                          ~(sigSum[1:sigWidth+1]).all()),
                           sigSum[1:sigWidth + 2].bool())),
             CDom_mainSig.eq(
                 (CDom_absSigSum<<intermed_CDom_CAlignDist)>>(sigWidth - 3)),
-- 
2.30.2