From 44af76221464559cd2d51a22cfb0dda7cc01d670 Mon Sep 17 00:00:00 2001
From: lkcl <lkcl@web>
Date: Sun, 3 May 2020 14:21:01 +0100
Subject: [PATCH]

---
 3d_gpu/architecture/regfile.mdwn | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/3d_gpu/architecture/regfile.mdwn b/3d_gpu/architecture/regfile.mdwn
index cd735fc3b..983e8c448 100644
--- a/3d_gpu/architecture/regfile.mdwn
+++ b/3d_gpu/architecture/regfile.mdwn
@@ -11,4 +11,4 @@ The FP and Integer registers need to be a massive 128 x 64-bit.
 
 # Connectivity between regfiles and Function Units
 
-[[!img regfile_hilo_32_odd_even.reg]]
+[[!img regfile_hilo_32_odd_even.png]]
-- 
2.30.2