From 44b3b7a5fac66f9d146e4d0bf8847333ceae7a69 Mon Sep 17 00:00:00 2001 From: lkcl Date: Sun, 9 Oct 2022 23:47:34 +0100 Subject: [PATCH] --- openpower/sv/rfc/ls002.mdwn | 9 +-------- 1 file changed, 1 insertion(+), 8 deletions(-) diff --git a/openpower/sv/rfc/ls002.mdwn b/openpower/sv/rfc/ls002.mdwn index 67c83f629..0543db6b4 100644 --- a/openpower/sv/rfc/ls002.mdwn +++ b/openpower/sv/rfc/ls002.mdwn @@ -32,7 +32,6 @@ Instructions added fmvis - Floating-Point Move Immediate, Shifted fishmv - Floating-Point Immediate, Second-half Move - (Potentially 64-bit prefixed of the same) ``` **Submitter**: Luke Leighton (Libre-SOC) @@ -43,7 +42,6 @@ ``` Addition of two new FPR-based instructions - (potentially 3 if EXT001 Prefixed variants added) ``` **Impact on software**: @@ -74,11 +72,7 @@ and TLB lookup. Even quickly clearing an FPR to zero presently requires Load. is an immediate loading instruction. No FPR Load Operations alter `FPSCR`, neither does `lxvkq`, and on that basis neither should these instructions. -3. An EXT001 Variant which also save similar Data-Load and Data-TLB - lookups are mentioned for completeness but not included as part - of this RFC. Another Stakeholder with a vested interest in 64-bit - Prefixed instructions may wish to consider submitting them. -4. `fishmv` as a FRS-only Read-Modify-Write (instead of an unnecessary +3. `fishmv` as a FRS-only Read-Modify-Write (instead of an unnecessary FRS,FRA pair) saves five potential bits, making the difference between a 5-bit XO (VA/DX-Form) and requiring an entire Primary Opcode. @@ -170,7 +164,6 @@ corresponding to the contents of FRT. **This instruction performs a Read-Modify-Write on FRT.** In hardware, `fishmv` may be macro-op-fused with `fmvis`. - Programmer's note: The use of these two instructions is strategically similar to how `li` combined with `oris` may be used to construct 32-bit Integers. -- 2.30.2