From 44c677d1ebb24fb9137943afb6a9981d0b2c14ea Mon Sep 17 00:00:00 2001 From: Jakub Jelinek Date: Sun, 30 Aug 2020 14:15:45 +0200 Subject: [PATCH] x86: Fix up ssse3_pshufbv8qi splitter The constant pool size optimization I was testing resulted in various ICEs in gcc.target/i386/ testsuite, the problem is that the ssse3_pshufbv8qi splitter emits invalid RTL, in V4SImode 0xf7f7f7f7 CONST_INTs shouldn't appear, instead they should have been -0x8080809 (0xf7f7f7f7 sign extended into 64 bits). 2020-08-30 Jakub Jelinek * config/i386/sse.md (ssse3_pshufbv8qi): Use gen_int_mode instead of GEN_INT, and ix86_build_const_vector instead of gen_rtvec and gen_rtx_CONT_VECTOR. --- gcc/config/i386/sse.md | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 44aa61d87fb..5e26e9c5aa2 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -16938,11 +16938,8 @@ GET_MODE (operands[2])); operands[4] = lowpart_subreg (V16QImode, operands[3], GET_MODE (operands[3])); - rtvec par = gen_rtvec (4, GEN_INT (0xf7f7f7f7), - GEN_INT (0xf7f7f7f7), - GEN_INT (0xf7f7f7f7), - GEN_INT (0xf7f7f7f7)); - rtx vec_const = gen_rtx_CONST_VECTOR (V4SImode, par); + rtx vec_const = ix86_build_const_vector (V4SImode, true, + gen_int_mode (0xf7f7f7f7, SImode)); operands[5] = force_const_mem (V4SImode, vec_const); } [(set_attr "mmx_isa" "native,sse_noavx,avx") -- 2.30.2