From 44d144609a2420bcc7c75f0e759f30379188ef71 Mon Sep 17 00:00:00 2001 From: lkcl Date: Sun, 21 Mar 2021 21:45:19 +0000 Subject: [PATCH] --- openpower/sv/setvl.mdwn | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/openpower/sv/setvl.mdwn b/openpower/sv/setvl.mdwn index e2dd83adf..aac1c47d7 100644 --- a/openpower/sv/setvl.mdwn +++ b/openpower/sv/setvl.mdwn @@ -45,9 +45,9 @@ Form: SVL-Form (see [[isatables/fields.text]]) | 0.5|6.10|11.15|16..23 | 24.25 | 26...30 |31| name | | -- | -- | --- | ------ | ------ | ------- |--| ------- | -|OPCD| RT | RA | SVi // | vs ms | XO[0:4] |Rc| setvl | +|OPCD| RT | RA | SVi / | vs ms | XO[0:4] |Rc| setvl | -Note that the immediate (`SVi`) spans 7 bits (16 to 22), and that bit 22 and 23 is reserved and must be zero. Setting bit 22 or 23 causes an illegal exception. +Note that the immediate (`SVi`) spans 7 bits (16 to 22), and that bit 23 is reserved and must be zero. Setting bit 23 to 1 causes an illegal exception. `ms` - bit 25 - allows for setting of MVL. `vs` - bit 24 - allows for setting of VL. -- 2.30.2