From 44ddad7166ca49e4608aa26e05e23465a4108b75 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Fri, 31 Dec 2021 14:02:09 +0000 Subject: [PATCH] manually patch in nmigen-yosys --- nmigen/back/verilog.py | 39 ++++----------------------------------- 1 file changed, 4 insertions(+), 35 deletions(-) diff --git a/nmigen/back/verilog.py b/nmigen/back/verilog.py index ca025b1..367488d 100644 --- a/nmigen/back/verilog.py +++ b/nmigen/back/verilog.py @@ -4,20 +4,6 @@ from . import rtlil __all__ = ["YosysError", "convert", "convert_fragment"] -class YosysError(Exception): - pass - - -def _yosys_version(): - yosys_path = require_tool("yosys") - version = subprocess.check_output([yosys_path, "-V"], encoding="utf-8") - # If Yosys is built with Verific, then Verific license information is printed first. - # See below for details. - m = re.search(r"^Yosys ([\d.]+)(?:\+(\d+))?", version, flags=re.M) - tag, offset = m[1], m[2] or 0 - return tuple(map(int, tag.split("."))), offset - - def _convert_rtlil_text(rtlil_text, *, strip_internal_attrs=False, write_verilog_opts=()): version, offset = _yosys_version() if version < (0, 9): @@ -31,7 +17,7 @@ def _convert_rtlil_text(rtlil_text, *, strip_internal_attrs=False, write_verilog attr_map.append("-remove nmigen.hierarchy") attr_map.append("-remove nmigen.decoding") - script = """ + return yosys.run(["-q", "-"], """ # Convert nMigen's RTLIL to readable Verilog. read_ilang <