From 44e40383a1152fbf6532d200a0624e038484affd Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 13 May 2020 22:19:54 +0100 Subject: [PATCH] comments (and whitespace --- libreriscv | 2 +- src/soc/alu/main_stage.py | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/libreriscv b/libreriscv index 7ced351c..29219bd5 160000 --- a/libreriscv +++ b/libreriscv @@ -1 +1 @@ -Subproject commit 7ced351c57a207e733bc8c95c923cbfe91d31831 +Subproject commit 29219bd53d45768c6f57a876a78c5758b29bd7d1 diff --git a/src/soc/alu/main_stage.py b/src/soc/alu/main_stage.py index 1231aeae..f5347d3f 100644 --- a/src/soc/alu/main_stage.py +++ b/src/soc/alu/main_stage.py @@ -61,6 +61,8 @@ class ALUMainStage(PipeModBase): #### xor #### with m.Case(InternalOp.OP_XOR): comb += self.o.o.eq(self.i.a ^ self.i.b) + + #### exts (sign-extend) #### with m.Case(InternalOp.OP_EXTS): with m.If(self.i.ctx.op.data_len == 1): comb += self.o.o.eq(Cat(self.i.a[0:8], @@ -71,8 +73,6 @@ class ALUMainStage(PipeModBase): with m.If(self.i.ctx.op.data_len == 4): comb += self.o.o.eq(Cat(self.i.a[0:32], Repl(self.i.a[31], 64-32))) - - ###### sticky overflow and context, both pass-through ##### -- 2.30.2