From 44e83151f723d851b50f57d58f16f7ca653f295e Mon Sep 17 00:00:00 2001 From: lkcl Date: Sun, 20 Dec 2020 18:22:55 +0000 Subject: [PATCH] --- openpower/sv/svp_rewrite/svp64.mdwn | 38 ++++++++++++++--------------- 1 file changed, 19 insertions(+), 19 deletions(-) diff --git a/openpower/sv/svp_rewrite/svp64.mdwn b/openpower/sv/svp_rewrite/svp64.mdwn index 8ba8f9a80..3d3c6eff8 100644 --- a/openpower/sv/svp_rewrite/svp64.mdwn +++ b/openpower/sv/svp_rewrite/svp64.mdwn @@ -30,6 +30,25 @@ v3.0/1B instructions covered by the prefix are "unaltered". This is termed `scal Note that this is completely different from when VL=0. VL=0 turns all operations under its influence into `nops`, whereas when VL=1 and the SV prefix is all zeros, the operation simply acts as if SV had not been applied at all to the instruction (an "identity operation"). +# Register Naming + +SV Registers are simply the INT, FP and CR register files extended +linearly to larger sizes. Thus, the integer regfile in standard scalar +OpenPOWER v3.0B and v3.1B is r0 to r31: SV extends this as r0 to r127. +Likewise FP registers are extended to 128 (fp0 to fp127), and CRs are +extended to 64 entries, CR0 thru CR63. + +The names of the registers therefore reflects a simple linear extension +of the OpenPOWER v3.0B / v3.1B register naming, and in hardware this +would be reflected by a linear increase in the size of the underlying +SRAM used for the regfiles. + +Note: when an EXTRA field (defined below) is zero, SV is deliberately designed +so that the register fields are identical to as if SV was not in effect +i.e. under these circumstances (EXTRA=0) the register field names RA, +RB etc. are interpreted and treated as v3.0B / v3.1B scalar registers. This is part of +`scalar identity behaviour` described above. + # Remapped Encoding (`RM[0:23]`) To allow relatively easy remapping of which portions of the Prefix Opcode @@ -515,25 +534,6 @@ Additional unusual capabilities of Twin Predication include a back-to-back version of VCOMPRESS-VEXPAND which is effectively the ability to do an ordered multiple VINSERT. -# Register Naming - -SV Registers are simply the INT, FP and CR register files extended -linearly to larger sizes. Thus, the integer regfile in standard scalar -OpenPOWER v3.0B and v3.1B is r0 to r31: SV extends this as r0 to r127. -Likewise FP registers are extended to 128 (fp0 to fp127), and CRs are -extended to 64 entries, CR0 thru CR63. - -The names of the registers therefore reflects a simple linear extension -of the OpenPOWER v3.0B / v3.1B register naming, and in hardware this -would be reflected by a linear increase in the size of the underlying -SRAM used for the regfiles. - -Note: when the EXTRA fields are all zero, SV is deliberately designed -so that the register fields are identical to as if SV was not in effect -i.e. under these circumstances (EXTRA=0) the register field names RA, -RB etc. are interpreted as v3.0B / v3.1B scalar registers. This is termed -`scalar identity behaviour` - # CR Operations CRs are slightly more involved than INT or FP registers due to the -- 2.30.2