From 451949c34085f6317c8822e9d596ce97e3bba8a7 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 14 Apr 2022 19:45:41 +0100 Subject: [PATCH] reduce versa_ecp5 clock freq to 50 mhz, reduce bit-width of XICS addressing --- hello_world/Makefile | 3 ++- hello_world/hello_world.c | 41 +++++++++++++++++++++++++++++++++++++++ src/ls2.py | 6 +++--- 3 files changed, 46 insertions(+), 4 deletions(-) diff --git a/hello_world/Makefile b/hello_world/Makefile index 88c2fb7..50f0391 100644 --- a/hello_world/Makefile +++ b/hello_world/Makefile @@ -5,7 +5,8 @@ ifneq ("$(ARCH)", "ppc64le") endif endif -BOOT_INIT_BASE ?= 0xf0000000 # at QSPI address +#BOOT_INIT_BASE ?= 0xf0000000 # at QSPI address +BOOT_INIT_BASE ?= 0x00600000 # inside DRAM address space # BOOT_INIT_BASE ?= 0xff000000 # at ROM hi address (with coldboot firmware) # BOOT_INIT_BASE ?= 0x0 # start at zero (usual) diff --git a/hello_world/hello_world.c b/hello_world/hello_world.c index 0f08631..a9d074f 100644 --- a/hello_world/hello_world.c +++ b/hello_world/hello_world.c @@ -15,12 +15,53 @@ static char mw_logo[] = " ;..; \n" " `ww' \n"; +static inline uint32_t readl(unsigned long addr) +{ + uint32_t val; + __asm__ volatile("sync; lwzcix %0,0,%1" : "=r" (val) : "r" (addr) : "memory"); + return val; +} + +static inline void writel(uint32_t val, unsigned long addr) +{ + __asm__ volatile("sync; stwcix %0,0,%1" : : "r" (val), "r" (addr) : "memory"); +} + +void uart_writeuint32(uint32_t val) { + const char lut[] = { '0', '1', '2', '3', '4', '5', '6', '7', + '8', '9', 'A', 'B', 'C', 'D', 'E', 'F' }; + uint8_t *val_arr = (uint8_t*)(&val); + size_t i; + + for (i = 0; i < 4; i++) { + putchar(lut[(val_arr[3-i] >> 4) & 0xF]); + putchar(lut[val_arr[3-i] & 0xF]); + } +} + + int main(void) { console_init(); puts(mw_logo); + volatile uint32_t *sram = 0x0; + int count = 26; + puts("writing\n"); + for (int i = 0; i < count; i++) { + uart_writeuint32(i); + puts("\n"); + writel(0xBEEF0000+i, &(sram[1<