From 45311906ce2747585884d737cb23e0ed3d1e4718 Mon Sep 17 00:00:00 2001 From: lkcl Date: Fri, 11 Dec 2020 02:06:18 +0000 Subject: [PATCH] --- openpower/sv/svp_rewrite/svp64.mdwn | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openpower/sv/svp_rewrite/svp64.mdwn b/openpower/sv/svp_rewrite/svp64.mdwn index e1970d82e..ece821324 100644 --- a/openpower/sv/svp_rewrite/svp64.mdwn +++ b/openpower/sv/svp_rewrite/svp64.mdwn @@ -32,7 +32,7 @@ defined in the Prefix Fields section. ## MASK Encoding -TODO: split out (remove) bit 3 as separate so that twin predication can use the same encoding, and split the table into 2 halves. The bit currently 3 becomes a separate (standalone) field (see [discussion]) that selects *both* src and dest predication as CR based or both as INT based. This saves one bit and makes things less complex. +TODO: split out (remove) bit 3 as separate so that twin predication can use the same encoding, and split the table into 2 halves. The bit currently 3 becomes a separate (standalone) field (see [discussion]) that selects *both* src and dest predication as CR based or both as INT based. This saves one bit and makes things less complex to implement in hardware. Integer based predication. Twin predication uses the same encoding thus allowing either the same register (r3 or r10) to be used for both src and dest, or different regs (one for src, one for dest) -- 2.30.2