From 4572cbac3f49608534bba9e54367f759eff6c667 Mon Sep 17 00:00:00 2001 From: Thiago Jung Bauermann Date: Thu, 19 Aug 2010 17:52:49 +0000 Subject: [PATCH] * gdb.arch/vsx-regs.exp: Remove wrong comment about testing AltiVec registers. Update data sets with the new v2_double element in the VSX register union. Add vector_register3_vr data set for the AltiVec registers. Use gdb_test_no_output instead of send_gdb. --- gdb/testsuite/ChangeLog | 7 +++++++ gdb/testsuite/gdb.arch/vsx-regs.exp | 20 ++++++++++---------- 2 files changed, 17 insertions(+), 10 deletions(-) diff --git a/gdb/testsuite/ChangeLog b/gdb/testsuite/ChangeLog index bf19fd415f0..a75d2574254 100644 --- a/gdb/testsuite/ChangeLog +++ b/gdb/testsuite/ChangeLog @@ -1,3 +1,10 @@ +2010-08-19 Thiago Jung Bauermann + + * gdb.arch/vsx-regs.exp: Remove wrong comment about testing AltiVec + registers. Update data sets with the new v2_double element in the + VSX register union. Add vector_register3_vr data set for the AltiVec + registers. Use gdb_test_no_output instead of send_gdb. + 2010-08-19 Pedro Alves * gdb.python/py-shared.exp: New file, factored out from diff --git a/gdb/testsuite/gdb.arch/vsx-regs.exp b/gdb/testsuite/gdb.arch/vsx-regs.exp index f310a6f255a..f515df7348e 100644 --- a/gdb/testsuite/gdb.arch/vsx-regs.exp +++ b/gdb/testsuite/gdb.arch/vsx-regs.exp @@ -14,8 +14,6 @@ # along with this program. If not, see . # -# Tests for Powerpc AltiVec register setting and fetching - if $tracelevel then { strace $tracelevel } @@ -66,11 +64,13 @@ if ![runto_main] then { # Data sets used throughout the test -set vector_register1 ".uint128 = 0x3ff4cccccccccccc0000000000000000, v4_float = .0x1, 0xf99999a0, 0x0, 0x0., v4_int32 = .0x3ff4cccc, 0xcccccccc, 0x0, 0x0., v8_int16 = .0x3ff4, 0xcccc, 0xcccc, 0xcccc, 0x0, 0x0, 0x0, 0x0., v16_int8 = .0x3f, 0xf4, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0.." +set vector_register1 ".uint128 = 0x3ff4cccccccccccc0000000000000000, v2_double = .0x1, 0x0., v4_float = .0x1, 0xf99999a0, 0x0, 0x0., v4_int32 = .0x3ff4cccc, 0xcccccccc, 0x0, 0x0., v8_int16 = .0x3ff4, 0xcccc, 0xcccc, 0xcccc, 0x0, 0x0, 0x0, 0x0., v16_int8 = .0x3f, 0xf4, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0.." + +set vector_register2 "uint128 = 0xdeadbeefdeadbeefdeadbeefdeadbeef, v2_double = .0x1, 0x1., v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = .0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef., v8_int16 = .0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef., v16_int8 = .0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef.." -set vector_register2 "uint128 = 0xdeadbeefdeadbeefdeadbeefdeadbeef, v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = .0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef., v8_int16 = .0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef., v16_int8 = .0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef.." +set vector_register3 ".uint128 = 0x00000001000000010000000100000001, v2_double = .0x0, 0x0., v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = .0x1, 0x1, 0x1, 0x1., v8_int16 = .0x0, 0x1, 0x0, 0x1, 0x0, 0x1, 0x0, 0x1., v16_int8 = .0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1.." -set vector_register3 ".uint128 = 0x00000001000000010000000100000001, v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = .0x1, 0x1, 0x1, 0x1., v8_int16 = .0x0, 0x1, 0x0, 0x1, 0x0, 0x1, 0x0, 0x1., v16_int8 = .0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1.." +set vector_register3_vr ".uint128 = 0x00000001000000010000000100000001, v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = .0x1, 0x1, 0x1, 0x1., v8_int16 = .0x0, 0x1, 0x0, 0x1, 0x0, 0x1, 0x0, 0x1., v16_int8 = .0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1.." set float_register ".raw 0xdeadbeefdeadbeef." @@ -78,7 +78,7 @@ set float_register ".raw 0xdeadbeefdeadbeef." # 1: Set F0~F31 registers and check if it reflects on VS0~VS31. for {set i 0} {$i < 32} {incr i 1} { - send_gdb "set \$f$i = 1\.3" + gdb_test_no_output "set \$f$i = 1\.3" } for {set i 0} {$i < 32} {incr i 1} { @@ -88,7 +88,7 @@ for {set i 0} {$i < 32} {incr i 1} { # 2: Set VS0~VS31 registers and check if it reflects on F0~F31. for {set i 0} {$i < 32} {incr i 1} { for {set j 0} {$j < 4} {incr j 1} { - send_gdb "set \$vs$i.v4_int32\[$j\] = 0xdeadbeef" + gdb_test_no_output "set \$vs$i.v4_int32\[$j\] = 0xdeadbeef" } } @@ -105,7 +105,7 @@ for {set i 0} {$i < 32} {incr i 1} { # 1: Set VR0~VR31 registers and check if it reflects on VS32~VS63. for {set i 0} {$i < 32} {incr i 1} { for {set j 0} {$j < 4} {incr j 1} { - send_gdb "set \$vr$i.v4_int32\[$j\] = 1" + gdb_test_no_output "set \$vr$i.v4_int32\[$j\] = 1" } } @@ -115,12 +115,12 @@ for {set i 32} {$i < 64} {incr i 1} { # 2: Set VS32~VS63 registers and check if it reflects on VR0~VR31. for {set i 32} {$i < 64} {incr i 1} { for {set j 0} {$j < 4} {incr j 1} { - send_gdb "set \$vs$i.v4_int32\[$j\] = 1" + gdb_test_no_output "set \$vs$i.v4_int32\[$j\] = 1" } } for {set i 0} {$i < 32} {incr i 1} { - gdb_test "info reg vr$i" "vr$i.*$vector_register3" "info reg vr$i" + gdb_test "info reg vr$i" "vr$i.*$vector_register3_vr" "info reg vr$i" } set escapedfilename [string_to_regexp ${objdir}/${subdir}/vsx-core.test] -- 2.30.2