From 458cfc862325e256706d70eb7ee6f5fa012668a9 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Mon, 5 Dec 2011 00:16:44 +0100 Subject: [PATCH] CSR bus definitions --- migen/bus/__init__.py | 0 migen/bus/csr.py | 35 ++++++++++++++++++++++++++++++ test.py | 50 ------------------------------------------- 3 files changed, 35 insertions(+), 50 deletions(-) create mode 100644 migen/bus/__init__.py create mode 100644 migen/bus/csr.py delete mode 100644 test.py diff --git a/migen/bus/__init__.py b/migen/bus/__init__.py new file mode 100644 index 00000000..e69de29b diff --git a/migen/bus/csr.py b/migen/bus/csr.py new file mode 100644 index 00000000..cd06436c --- /dev/null +++ b/migen/bus/csr.py @@ -0,0 +1,35 @@ +from migen.fhdl import structure as f +from functools import partial + +class Master: + def __init__(self): + d = partial(f.Declare, self) + d("a_o", f.BV(16)) + d("we_o") + d("d_o", f.BV(32)) + d("d_i", f.BV(32)) + +class Slave: + def __init__(self): + d = partial(f.Declare, self) + d("a_i", f.BV(16)) + d("we_i") + d("d_i", f.BV(32)) + d("d_o", f.BV(32)) + +class Interconnect: + def __init__(self, master, slaves): + self.master = master + self.slaves = slaves + + def GetFragment(self): + a = f.Assign + comb = [] + rb = f.Constant(0, f.BV(32)) + for slave in self.slaves: + comb.append(a(slave.a_i, self.master.a_o)) + comb.append(a(slave.we_i, self.master.we_o)) + comb.append(a(slave.d_i, self.master.d_o)) + rb = rb | slave.d_o + comb.append(a(master.d_i, rb)) + return f.Fragment(comb) \ No newline at end of file diff --git a/test.py b/test.py deleted file mode 100644 index 0531ad42..00000000 --- a/test.py +++ /dev/null @@ -1,50 +0,0 @@ -from migen.fhdl import structure as f -from migen.fhdl import verilog -from functools import partial - -class Divider: - def __init__(self, w): - self.w = w - - d = partial(f.Declare, self) - - d("start_i") - d("dividend_i", f.BV(w)) - d("divisor_i", f.BV(w)) - d("ready_o") - d("quotient_o", f.BV(w)) - d("remainder_o", f.BV(w)) - - d("_qr", f.BV(2*w)) - d("_counter", f.BV(f.BitsFor(w))) - d("_divisor_r", f.BV(w)) - d("_diff", f.BV(w+1)) - - def GetFragment(self): - a = f.Assign - comb = [ - a(self.quotient_o, self._qr[:self.w]), - a(self.remainder_o, self._qr[self.w:]), - a(self.ready_o, self._counter == f.Constant(0, self._counter.bv)), - a(self._diff, self.remainder_o - self._divisor_r) - ] - sync = [ - f.If(self.start_i == 1, [ - a(self._counter, self.w), - a(self._qr, self.dividend_i), - a(self._divisor_r, self.divisor_i) - ], [ - f.If(self.ready_o == 0, [ - f.If(self._diff[self.w] == 1, - [a(self._qr, f.Cat(0, self._qr[:2*self.w-1]))], - [a(self._qr, f.Cat(1, self._qr[:self.w-1], self._diff[:self.w]))]), - a(self._counter, self._counter - f.Constant(1, self._counter.bv)), - ]) - ]) - ] - return f.Fragment(comb, sync) - -d = Divider(32) -f = d.GetFragment() -o = verilog.Convert(f, {d.start_i, d.dividend_i, d.divisor_i}, {d.ready_o, d.quotient_o, d.remainder_o}) -print(o) \ No newline at end of file -- 2.30.2