From 45b28ac856800f13c9759aa52994f605ab4becaa Mon Sep 17 00:00:00 2001 From: whitequark Date: Thu, 22 Oct 2020 13:23:06 +0000 Subject: [PATCH] hdl.dsl: error on Elif immediately nested in an If. I.e. on this code, which is currently not only wrongly accepted but also results in completely unexpected RTL: with m.If(...): with m.Elif(...): ... Fixes #500. --- nmigen/hdl/dsl.py | 2 +- tests/test_hdl_dsl.py | 8 ++++++++ 2 files changed, 9 insertions(+), 1 deletion(-) diff --git a/nmigen/hdl/dsl.py b/nmigen/hdl/dsl.py index 12081ac..fd20774 100644 --- a/nmigen/hdl/dsl.py +++ b/nmigen/hdl/dsl.py @@ -249,7 +249,7 @@ class Module(_ModuleBuilderRoot, Elaboratable): cond = self._check_signed_cond(cond) src_loc = tracer.get_src_loc(src_loc_at=1) if_data = self._get_ctrl("If") - if if_data is None: + if if_data is None or len(if_data["tests"]) == 0: raise SyntaxError("Elif without preceding If") try: _outer_case, self._statements = self._statements, [] diff --git a/tests/test_hdl_dsl.py b/tests/test_hdl_dsl.py index 8ec1be7..6c5f117 100644 --- a/tests/test_hdl_dsl.py +++ b/tests/test_hdl_dsl.py @@ -266,6 +266,14 @@ class DSLTestCase(FHDLTestCase): with m.Elif(self.s2): pass + def test_Elif_wrong_nested(self): + m = Module() + with m.If(self.s1): + with self.assertRaisesRegex(SyntaxError, + r"^Elif without preceding If$"): + with m.Elif(self.s2): + pass + def test_Else_wrong(self): m = Module() with self.assertRaisesRegex(SyntaxError, -- 2.30.2