From 45c2a5f87694a83e0cf96477ede02567a93b32a8 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 12 Jun 2019 08:34:06 -0700
Subject: [PATCH] Add shregmap -tech xilinx test

---
 tests/various/shregmap.v  | 28 +++++++++++++++++++++++++++-
 tests/various/shregmap.ys | 37 ++++++++++++++++++++++++++++++++++++-
 2 files changed, 63 insertions(+), 2 deletions(-)

diff --git a/tests/various/shregmap.v b/tests/various/shregmap.v
index 56e05c2c0..604c2c976 100644
--- a/tests/various/shregmap.v
+++ b/tests/various/shregmap.v
@@ -1,4 +1,4 @@
-module shregmap_test(input i, clk, output [1:0] q);
+module shregmap_static_test(input i, clk, output [1:0] q);
 reg head = 1'b0;
 reg [3:0] shift1 = 4'b0000;
 reg [3:0] shift2 = 4'b0000;
@@ -20,3 +20,29 @@ always @(posedge C)
     r <= { r[DEPTH-2:0], D };
 assign Q = r[DEPTH-1];
 endmodule
+
+module shregmap_variable_test(input i, clk, input [1:0] l1, l2, output [1:0] q);
+reg head = 1'b0;
+reg [3:0] shift1 = 4'b0000;
+reg [3:0] shift2 = 4'b0000;
+
+always @(posedge clk) begin
+    head <= i;
+    shift1 <= {shift1[2:0], head};
+    shift2 <= {shift2[2:0], head};
+end
+
+assign q = {shift2[l2], shift1[l1]};
+endmodule
+
+module $__XILINX_SHREG_(input C, D, input [1:0] L, output Q);
+parameter CLKPOL = 1;
+parameter ENPOL = 1;
+parameter DEPTH = 1;
+parameter [DEPTH-1:0] INIT = {DEPTH{1'b0}};
+reg [DEPTH-1:0] r = INIT;
+wire clk = C ^ CLKPOL;
+always @(posedge C)
+    r <= { r[DEPTH-2:0], D };
+assign Q = r[L];
+endmodule
diff --git a/tests/various/shregmap.ys b/tests/various/shregmap.ys
index ca7f47015..d644a88aa 100644
--- a/tests/various/shregmap.ys
+++ b/tests/various/shregmap.ys
@@ -1,6 +1,8 @@
 read_verilog shregmap.v
+design -save read
+
 design -copy-to model $__SHREG_DFF_P_
-hierarchy -top shregmap_test
+hierarchy -top shregmap_static_test
 prep
 design -save gold
 
@@ -29,3 +31,36 @@ stat
 
 design -load gate
 stat
+
+##########
+
+design -load read
+design -copy-to model $__XILINX_SHREG_
+hierarchy -top shregmap_variable_test
+prep
+design -save gold
+
+simplemap t:$dff t:$dffe
+shregmap -tech xilinx
+
+stat
+# show -width
+write_verilog -noexpr -norename
+select -assert-count 1 t:$_DFF_P_
+select -assert-count 2 t:$__XILINX_SHREG_
+
+design -stash gate
+
+design -import gold -as gold
+design -import gate -as gate
+design -copy-from model -as $__XILINX_SHREG_ \$__XILINX_SHREG_
+prep
+
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+sat -verify -prove-asserts -show-ports -seq 5 miter
+
+design -load gold
+stat
+
+design -load gate
+stat
-- 
2.30.2