From 45d69db4ce2086b86fb26ca5ee0bd6cdabb8d694 Mon Sep 17 00:00:00 2001 From: Dmitry Selyutin Date: Sun, 18 Sep 2022 11:26:34 +0300 Subject: [PATCH] power_insn: decouple common normal and ld/st RM --- src/openpower/decoder/power_insn.py | 36 ++++++++--------------------- 1 file changed, 9 insertions(+), 27 deletions(-) diff --git a/src/openpower/decoder/power_insn.py b/src/openpower/decoder/power_insn.py index d092bd16..9f80d3a3 100644 --- a/src/openpower/decoder/power_insn.py +++ b/src/openpower/decoder/power_insn.py @@ -1300,7 +1300,7 @@ class BaseRM(_Mapping): yield f"{indent}{', '.join(map(str, members))}" -class NormalBaseRM(BaseRM): +class NormalLDSTBaseRM(BaseRM): @property def specifiers(self): ew = int(self.elwidth) @@ -1315,6 +1315,10 @@ class NormalBaseRM(BaseRM): yield from super().specifiers +class NormalBaseRM(NormalLDSTBaseRM): + pass + + class NormalSimpleRM(NormalBaseRM): """normal: simple mode""" dz: BaseRM.mode[3] @@ -1427,19 +1431,8 @@ class NormalRM(NormalBaseRM): prrc0: NormalPredResultRc0RM -class LDSTImmBaseRM(BaseRM): - @property - def specifiers(self): - ew = int(self.elwidth) - if ew != 0b00: - ew = { - 0b11: "8", - 0b10: "16", - 0b01: "32", - }[ew] - yield f"ew={ew}" - - yield from super().specifiers +class LDSTImmBaseRM(NormalLDSTBaseRM): + pass class LDSTImmSimpleRM(LDSTImmBaseRM): @@ -1510,19 +1503,8 @@ class LDSTImmRM(LDSTImmBaseRM): prrc0: LDSTImmPredResultRc0RM -class LDSTIdxBaseRM(BaseRM): - @property - def specifiers(self): - ew = int(self.elwidth) - if ew != 0b00: - ew = { - 0b11: "8", - 0b10: "16", - 0b01: "32", - }[ew] - yield f"ew={ew}" - - yield from super().specifiers +class LDSTIdxBaseRM(NormalLDSTBaseRM): + pass class LDSTIdxSimpleRM(LDSTIdxBaseRM): -- 2.30.2