From 45e9a42c7ea5a260fdbf29e0933410d5ee4776fe Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Tue, 21 Aug 2018 19:10:22 +0200 Subject: [PATCH] soc_core: add cpu_endianness --- litex/soc/integration/cpu_interface.py | 1 + litex/soc/integration/soc_core.py | 2 ++ 2 files changed, 3 insertions(+) diff --git a/litex/soc/integration/cpu_interface.py b/litex/soc/integration/cpu_interface.py index ad4e8a33..bc934cf3 100644 --- a/litex/soc/integration/cpu_interface.py +++ b/litex/soc/integration/cpu_interface.py @@ -6,6 +6,7 @@ from migen import * from litex.soc.interconnect.csr import CSRStatus cpu_endianness = { + None: "big", "lm32": "big", "or1k": "big", "picorv32": "little", diff --git a/litex/soc/integration/soc_core.py b/litex/soc/integration/soc_core.py index 61e58687..6a7bbd40 100644 --- a/litex/soc/integration/soc_core.py +++ b/litex/soc/integration/soc_core.py @@ -7,6 +7,7 @@ from litex.soc.cores import identifier, timer, uart from litex.soc.cores.cpu import lm32, mor1kx, picorv32, vexriscv from litex.soc.interconnect.csr import * from litex.soc.interconnect import wishbone, csr_bus, wishbone2csr +from litex.soc.integration.cpu_interface import cpu_endianness __all__ = ["mem_decoder", "SoCCore", "soc_core_args", "soc_core_argdict"] @@ -105,6 +106,7 @@ class SoCCore(Module): self.cpu_type = cpu_type self.cpu_variant = cpu_variant + self.cpu_endianness = cpu_endianness[cpu_type] if integrated_rom_size: cpu_reset_address = self.mem_map["rom"] self.cpu_reset_address = cpu_reset_address -- 2.30.2