From 461b22d416c5c9d93ea2417f82e5542c9e52bf03 Mon Sep 17 00:00:00 2001 From: lkcl Date: Mon, 8 Aug 2022 12:45:06 +0100 Subject: [PATCH] --- openpower/sv/svp64/appendix.mdwn | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/openpower/sv/svp64/appendix.mdwn b/openpower/sv/svp64/appendix.mdwn index 236abd5a0..4e3182144 100644 --- a/openpower/sv/svp64/appendix.mdwn +++ b/openpower/sv/svp64/appendix.mdwn @@ -658,7 +658,11 @@ Thus the new VL comprises a contiguous vector of results, all of which pass the testing criteria (equal to zero, less than zero). The CR-based data-driven fail-on-first is new and not found in ARM -SVE or RVV. It is extremely useful for reducing instruction count, +SVE or RVV. At the same time it is also "old" because it is a generalisation +of the Z80 +[Block compare](https://rvbelzen.tripod.com/z80prgtemp/z80prg04.htm) +instructions, especially + It is extremely useful for reducing instruction count, however requires speculative execution involving modifications of VL to get high performance implementations. An additional mode (RC1=1) effectively turns what would otherwise be an arithmetic operation -- 2.30.2