From 4644d5a985a93f7031ed8d75b13055594aeb5ac3 Mon Sep 17 00:00:00 2001
From: lkcl <lkcl@web>
Date: Sat, 7 May 2022 12:35:07 +0100
Subject: [PATCH]

---
 openpower/sv/SimpleV_rationale.mdwn | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/openpower/sv/SimpleV_rationale.mdwn b/openpower/sv/SimpleV_rationale.mdwn
index f27479779..1c63c2c55 100644
--- a/openpower/sv/SimpleV_rationale.mdwn
+++ b/openpower/sv/SimpleV_rationale.mdwn
@@ -335,7 +335,7 @@ Remarkably, very little: the devil is in the details though.
   emergent characteristic from the carry-in, carry-out capability of
   Power ISA `adde` instruction. `sv.adde` as a BigNum add
   naturally emerges from the
-  sequential chaining of these scalar instructions.
+  sequential carry-flag chaining of these scalar instructions.
 * The Condition Register Fields of the Power ISA make a great candidate
   for use as Predicate Masks, particularly when combined with
   Vectorised `cmp` and Vectorised `crand`, `crxor` etc.
-- 
2.30.2