From 46505821ec00cead429af990358d2a4dd28e87b6 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Thu, 8 Nov 2007 18:51:50 -0800 Subject: [PATCH] ISA parser: Make the isa parser generate MaxInstSrcRegs and MaxInstDestRegs. --HG-- extra : convert_revision : 8c35891945c6b4ebc320f0c88a7a0449f3c4b4d5 --- src/arch/SConscript | 2 +- src/arch/alpha/isa_traits.hh | 7 +++---- src/arch/isa_parser.py | 34 ++++++++++++++++++++++++++++++++++ src/arch/mips/isa_traits.hh | 7 +++---- src/arch/sparc/isa_traits.hh | 7 +++---- src/arch/x86/isa_traits.hh | 7 +++---- 6 files changed, 47 insertions(+), 17 deletions(-) diff --git a/src/arch/SConscript b/src/arch/SConscript index e051c44af..66f93870e 100644 --- a/src/arch/SConscript +++ b/src/arch/SConscript @@ -97,7 +97,7 @@ execfile(cpu_models_file.srcnode().abspath) # Several files are generated from the ISA description. # We always get the basic decoder and header file. -isa_desc_gen_files = [ 'decoder.cc', 'decoder.hh' ] +isa_desc_gen_files = [ 'decoder.cc', 'decoder.hh', 'max_inst_regs.hh' ] # We also get an execute file for each selected CPU model. isa_desc_gen_files += [CpuModel.dict[cpu].filename for cpu in env['CPU_MODELS']] diff --git a/src/arch/alpha/isa_traits.hh b/src/arch/alpha/isa_traits.hh index 53eea5f69..be1d1b8bb 100644 --- a/src/arch/alpha/isa_traits.hh +++ b/src/arch/alpha/isa_traits.hh @@ -35,6 +35,7 @@ namespace LittleEndianGuest {} #include "arch/alpha/ipr.hh" +#include "arch/alpha/max_inst_regs.hh" #include "arch/alpha/types.hh" #include "config/full_system.hh" #include "sim/host.hh" @@ -44,6 +45,8 @@ class StaticInstPtr; namespace AlphaISA { using namespace LittleEndianGuest; + using AlphaISAInst::MaxInstSrcRegs; + using AlphaISAInst::MaxInstDestRegs; // These enumerate all the registers for dependence tracking. enum DependenceTags { @@ -144,10 +147,6 @@ namespace AlphaISA const int TotalDataRegs = NumIntRegs + NumFloatRegs; - // Static instruction parameters - const int MaxInstSrcRegs = 3; - const int MaxInstDestRegs = 2; - // semantically meaningful register indices const int ZeroReg = 31; // architecturally meaningful // the rest of these depend on the ABI diff --git a/src/arch/isa_parser.py b/src/arch/isa_parser.py index fb398d152..25908e986 100755 --- a/src/arch/isa_parser.py +++ b/src/arch/isa_parser.py @@ -1573,6 +1573,8 @@ def buildOperandNameMap(userDict, lineno): global operandsWithExtRE operandsWithExtRE = re.compile(operandsWithExtREString, re.MULTILINE) +maxInstSrcRegs = 0 +maxInstDestRegs = 0 class OperandList: @@ -1636,6 +1638,12 @@ class OperandList: if self.memOperand: error(0, "Code block has more than one memory operand.") self.memOperand = op_desc + global maxInstSrcRegs + global maxInstDestRegs + if maxInstSrcRegs < self.numSrcRegs: + maxInstSrcRegs = self.numSrcRegs + if maxInstDestRegs < self.numDestRegs: + maxInstDestRegs = self.numDestRegs # now make a final pass to finalize op_desc fields that may depend # on the register enumeration for op_desc in self.items: @@ -1855,6 +1863,22 @@ namespace %(namespace)s { %(decode_function)s ''' +max_inst_regs_template = ''' +/* + * DO NOT EDIT THIS FILE!!! + * + * It was automatically generated from the ISA description in %(filename)s + */ + +namespace %(namespace)s { + + const int MaxInstSrcRegs = %(MaxInstSrcRegs)d; + const int MaxInstDestRegs = %(MaxInstDestRegs)d; + +} // namespace %(namespace)s + +''' + # Update the output file only if the new contents are different from # the current contents. Minimizes the files that need to be rebuilt @@ -1954,6 +1978,16 @@ def parse_isa_desc(isa_desc_file, output_dir): update_if_needed(output_dir + '/' + cpu.filename, file_template % vars()) + # The variable names here are hacky, but this will creat local variables + # which will be referenced in vars() which have the value of the globals. + global maxInstSrcRegs + MaxInstSrcRegs = maxInstSrcRegs + global maxInstDestRegs + MaxInstDestRegs = maxInstDestRegs + # max_inst_regs.hh + update_if_needed(output_dir + '/max_inst_regs.hh', \ + max_inst_regs_template % vars()) + # global list of CpuModel objects (see cpu_models.py) cpu_models = [] diff --git a/src/arch/mips/isa_traits.hh b/src/arch/mips/isa_traits.hh index 5d4403553..cc584faa8 100644 --- a/src/arch/mips/isa_traits.hh +++ b/src/arch/mips/isa_traits.hh @@ -32,6 +32,7 @@ #ifndef __ARCH_MIPS_ISA_TRAITS_HH__ #define __ARCH_MIPS_ISA_TRAITS_HH__ +#include "arch/mips/max_inst_regs.hh" #include "arch/mips/types.hh" #include "sim/host.hh" @@ -44,6 +45,8 @@ class StaticInstPtr; namespace MipsISA { using namespace LittleEndianGuest; + using MipsISAInst::MaxInstSrcRegs; + using MipsISAInst::MaxInstDestRegs; StaticInstPtr decodeInst(ExtMachInst); @@ -64,10 +67,6 @@ namespace MipsISA const int NumFloatArchRegs = 32; const int NumFloatSpecialRegs = 5; - // Static instruction parameters - const int MaxInstSrcRegs = 5; - const int MaxInstDestRegs = 4; - // semantically meaningful register indices const int ZeroReg = 0; const int AssemblerReg = 1; diff --git a/src/arch/sparc/isa_traits.hh b/src/arch/sparc/isa_traits.hh index 4f3d20606..133817eb5 100644 --- a/src/arch/sparc/isa_traits.hh +++ b/src/arch/sparc/isa_traits.hh @@ -33,6 +33,7 @@ #define __ARCH_SPARC_ISA_TRAITS_HH__ #include "arch/sparc/types.hh" +#include "arch/sparc/max_inst_regs.hh" #include "arch/sparc/sparc_traits.hh" #include "config/full_system.hh" #include "sim/host.hh" @@ -49,6 +50,8 @@ namespace SparcISA //This makes sure the big endian versions of certain functions are used. using namespace BigEndianGuest; + using SparcISAInst::MaxInstSrcRegs; + using SparcISAInst::MaxInstDestRegs; // SPARC has a delay slot #define ISA_HAS_DELAY_SLOT 1 @@ -76,10 +79,6 @@ namespace SparcISA // Some OS syscall use a second register (o1) to return a second value const int SyscallPseudoReturnReg = ArgumentReg[1]; - //XXX These numbers are bogus - const int MaxInstSrcRegs = 8; - const int MaxInstDestRegs = 9; - //8K. This value is implmentation specific; and should probably //be somewhere else. const int LogVMPageSize = 13; diff --git a/src/arch/x86/isa_traits.hh b/src/arch/x86/isa_traits.hh index 762f9b172..abb7694ed 100644 --- a/src/arch/x86/isa_traits.hh +++ b/src/arch/x86/isa_traits.hh @@ -59,6 +59,7 @@ #define __ARCH_X86_ISATRAITS_HH__ #include "arch/x86/intregs.hh" +#include "arch/x86/max_inst_regs.hh" #include "arch/x86/types.hh" #include "arch/x86/x86_traits.hh" #include "sim/host.hh" @@ -72,6 +73,8 @@ namespace X86ISA //This makes sure the little endian version of certain functions //are used. using namespace LittleEndianGuest; + using X86ISAInst::MaxInstSrcRegs; + using X86ISAInst::MaxInstDestRegs; // X86 does not have a delay slot #define ISA_HAS_DELAY_SLOT 0 @@ -121,10 +124,6 @@ namespace X86ISA // value const int SyscallPseudoReturnReg = INTREG_RDX; - //XXX These numbers are bogus - const int MaxInstSrcRegs = 10; - const int MaxInstDestRegs = 10; - //4k. This value is not constant on x86. const int LogVMPageSize = 12; const int VMPageSize = (1 << LogVMPageSize); -- 2.30.2