From 46608f7469d7d92d715cfe29195e4bd6b2e96545 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Tue, 2 May 2023 19:49:50 +0100 Subject: [PATCH] reserve writes in Issue Phase, add comment --- src/openpower/cyclemodel/inorder.py | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/src/openpower/cyclemodel/inorder.py b/src/openpower/cyclemodel/inorder.py index 525d81c6..c1f8c057 100644 --- a/src/openpower/cyclemodel/inorder.py +++ b/src/openpower/cyclemodel/inorder.py @@ -4,6 +4,16 @@ # Funded by NLnet # # Bugs: https://bugs.libre-soc.org/show_bug.cgi?id=1039 +""" + CPU: Fetch <- log file + | + Decode <- works out read/write regs + | + Issue <- checks read-regs, sets write-regs + | + Execute -> stages (countdown) clears write-regs + +""" class RegisterWrite(set): """RegisterWrite: contains the set of Read-after-Write Hazards. @@ -91,12 +101,15 @@ class Decode: def process_instructions(self, stall): if stall: return stall - insn, writeregs, readregs = self.stages[0] # get current instruction + # get current instruction + insn, writeregs, readregs = self.stages[0] # check that the readregs are all available reads_possible = self.cpu.reads_possible(readregs): stall = reads_possible != readregs # perform the "reads" that are possible in this cycle readregs.difference_update(reads_possible) + # and "Reserves" the writes + self.cpu.expect_write(writeregs) return stall -- 2.30.2