From 4663b943c6eec1006f160dbec0729511bc5d1838 Mon Sep 17 00:00:00 2001 From: Richard Sandiford Date: Tue, 7 Aug 2018 17:22:19 +0000 Subject: [PATCH] [AArch64] Fix -mlow-precision-div (PR 86838) The "@" handling broke -mlow-precision-div, because the scalar forms of the instruction were provided by a pattern that also provided FRECPX (and so were parameterised on an unspec code as well as a mode), while the SIMD versions had a dedicated FRECPE pattern. This patch moves the scalar FRECPE handling to the SIMD pattern too (as for FRECPS) and uses a separate pattern for FRECPX. The convention in aarch64-simd-builtins.def seemed to be to add comments only if the mapping wasn't obvious (i.e. not just sticking "aarch64_" on the beginning and "" on the end), so the patch deletes the reference to the combined pattern instead of rewording it. There didn't seem to be any coverage of -mlow-precision-div in the testsuite, so the patch adds some tests for it. 2018-08-07 Richard Sandiford gcc/ PR target/86838 * config/aarch64/iterators.md (FRECP, frecp_suffix): Delete. * config/aarch64/aarch64-simd.md (aarch64_frecp): Fold FRECPE into... (@aarch64_frecpe): ...here and the move FRECPX to... (aarch64_frecpx): ...this new pattern. * config/aarch64/aarch64-simd-builtins.def: Remove comment about aarch64_frecp. gcc/testsuite/ PR target/86838 * gcc.target/aarch64/frecpe_1.c: New test. * gcc.target/aarch64/frecpe_2.c: Likewise. From-SVN: r263362 --- gcc/ChangeLog | 11 +++++++++++ gcc/config/aarch64/aarch64-simd-builtins.def | 2 -- gcc/config/aarch64/aarch64-simd.md | 15 ++++++++------- gcc/config/aarch64/iterators.md | 4 ---- gcc/testsuite/ChangeLog | 6 ++++++ gcc/testsuite/gcc.target/aarch64/frecpe_1.c | 18 ++++++++++++++++++ gcc/testsuite/gcc.target/aarch64/frecpe_2.c | 18 ++++++++++++++++++ 7 files changed, 61 insertions(+), 13 deletions(-) create mode 100644 gcc/testsuite/gcc.target/aarch64/frecpe_1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/frecpe_2.c diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 66394b87d84..15baa0ce53d 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,14 @@ +2018-08-07 Richard Sandiford + + PR target/86838 + * config/aarch64/iterators.md (FRECP, frecp_suffix): Delete. + * config/aarch64/aarch64-simd.md + (aarch64_frecp): Fold FRECPE into... + (@aarch64_frecpe): ...here and the move FRECPX to... + (aarch64_frecpx): ...this new pattern. + * config/aarch64/aarch64-simd-builtins.def: Remove comment + about aarch64_frecp. + 2018-08-07 Martin Liska PR middle-end/83023 diff --git a/gcc/config/aarch64/aarch64-simd-builtins.def b/gcc/config/aarch64/aarch64-simd-builtins.def index c4a5d0dbcb2..980c90351b3 100644 --- a/gcc/config/aarch64/aarch64-simd-builtins.def +++ b/gcc/config/aarch64/aarch64-simd-builtins.def @@ -413,8 +413,6 @@ BUILTIN_VALL (BINOP, trn1, 0) BUILTIN_VALL (BINOP, trn2, 0) - /* Implemented by - aarch64_frecp. */ BUILTIN_GPF_F16 (UNOP, frecpe, 0) BUILTIN_GPF_F16 (UNOP, frecpx, 0) diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index 5591c7b5a6b..33fb9da1614 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -5879,21 +5879,22 @@ (define_insn "@aarch64_frecpe" - [(set (match_operand:VHSDF 0 "register_operand" "=w") - (unspec:VHSDF [(match_operand:VHSDF 1 "register_operand" "w")] + [(set (match_operand:VHSDF_HSDF 0 "register_operand" "=w") + (unspec:VHSDF_HSDF + [(match_operand:VHSDF_HSDF 1 "register_operand" "w")] UNSPEC_FRECPE))] "TARGET_SIMD" - "frecpe\\t%0., %1." + "frecpe\t%0, %1" [(set_attr "type" "neon_fp_recpe_")] ) -(define_insn "aarch64_frecp" +(define_insn "aarch64_frecpx" [(set (match_operand:GPF_F16 0 "register_operand" "=w") (unspec:GPF_F16 [(match_operand:GPF_F16 1 "register_operand" "w")] - FRECP))] + UNSPEC_FRECPX))] "TARGET_SIMD" - "frecp\\t%0, %1" - [(set_attr "type" "neon_fp_recp_")] + "frecpx\t%0, %1" + [(set_attr "type" "neon_fp_recpx_")] ) (define_insn "@aarch64_frecps" diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md index 450edea8ca0..a43956054e8 100644 --- a/gcc/config/aarch64/iterators.md +++ b/gcc/config/aarch64/iterators.md @@ -1537,8 +1537,6 @@ (define_int_iterator FCVT_F2FIXED [UNSPEC_FCVTZS UNSPEC_FCVTZU]) (define_int_iterator FCVT_FIXED2F [UNSPEC_SCVTF UNSPEC_UCVTF]) -(define_int_iterator FRECP [UNSPEC_FRECPE UNSPEC_FRECPX]) - (define_int_iterator CRC [UNSPEC_CRC32B UNSPEC_CRC32H UNSPEC_CRC32W UNSPEC_CRC32X UNSPEC_CRC32CB UNSPEC_CRC32CH UNSPEC_CRC32CW UNSPEC_CRC32CX]) @@ -1788,8 +1786,6 @@ (UNSPEC_UNPACKSLO "BYTES_BIG_ENDIAN") (UNSPEC_UNPACKULO "BYTES_BIG_ENDIAN")]) -(define_int_attr frecp_suffix [(UNSPEC_FRECPE "e") (UNSPEC_FRECPX "x")]) - (define_int_attr crc_variant [(UNSPEC_CRC32B "crc32b") (UNSPEC_CRC32H "crc32h") (UNSPEC_CRC32W "crc32w") (UNSPEC_CRC32X "crc32x") (UNSPEC_CRC32CB "crc32cb") (UNSPEC_CRC32CH "crc32ch") diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index a607ed60e30..c4aaa448fa1 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,9 @@ +2018-08-07 Richard Sandiford + + PR target/86838 + * gcc.target/aarch64/frecpe_1.c: New test. + * gcc.target/aarch64/frecpe_2.c: Likewise. + 2018-08-07 Paolo Carlini PR c++/59480, DR 136 diff --git a/gcc/testsuite/gcc.target/aarch64/frecpe_1.c b/gcc/testsuite/gcc.target/aarch64/frecpe_1.c new file mode 100644 index 00000000000..e79f80d3ead --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/frecpe_1.c @@ -0,0 +1,18 @@ +/* { dg-options "-Ofast -mlow-precision-div" } */ +/* { dg-do compile } */ + +float +f1 (float x) +{ + return 1 / x; +} + +/* { dg-final { scan-assembler {\tfrecpe\t(s[0-9]+), s0\n\tfrecps\t(s[0-9]+), \1, s0\n\tfmul\ts0, \1, \2\n} } } */ + +double +f2 (double x) +{ + return 1 / x; +} + +/* { dg-final { scan-assembler {\tfrecpe\t(d[0-9]+), d0\n\tfrecps\t(d[0-9]+), \1, d0\n\tfmul\t\1, \1, \2\n\tfrecps\t\2, \1, d0\n\tfmul\td0, \1, \2\n} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/frecpe_2.c b/gcc/testsuite/gcc.target/aarch64/frecpe_2.c new file mode 100644 index 00000000000..233817c26b2 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/frecpe_2.c @@ -0,0 +1,18 @@ +/* { dg-options "-Ofast -mlow-precision-div" } */ +/* { dg-do compile } */ + +float +f1 (float x, float y) +{ + return y / x; +} + +/* { dg-final { scan-assembler {\tfrecpe\t(s[0-9]+), s0\n\tfrecps\t(s[0-9]+), \1, s0\n\tfmul\t\1, \1, s1\n\tfmul\ts0, \1, \2\n} } } */ + +double +f2 (double x, double y) +{ + return y / x; +} + +/* { dg-final { scan-assembler {\tfrecpe\t(d[0-9]+), d0\n\tfrecps\t(d[0-9]+), \1, d0\n\tfmul\t\1, \1, \2\n\tfrecps\t\2, \1, d0\n\tfmul\t\1, \1, d1\n\tfmul\td0, \1, \2\n} } } */ -- 2.30.2