From 466567a09ef6119257ace960df4130e5a7a27eb5 Mon Sep 17 00:00:00 2001
From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 14 Jun 2022 12:34:09 +0100
Subject: [PATCH] add link to draft horizontal/vertical-first image

---
 openpower/sv/SimpleV_rationale.mdwn | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/openpower/sv/SimpleV_rationale.mdwn b/openpower/sv/SimpleV_rationale.mdwn
index 84eab2415..d16c79a2b 100644
--- a/openpower/sv/SimpleV_rationale.mdwn
+++ b/openpower/sv/SimpleV_rationale.mdwn
@@ -846,9 +846,6 @@ There is also no reason why this type of arrangement should not be deployed
 in Multi-Chip-Module (aka "Chiplet") form, giving all the advantages of
 the performance boost that goes with smaller line-drivers.
 
-
-Draft Image (placeholder):
-
 <img src="/openpower/sv/bridge_phy.svg" width=600 />
 
 # Transparently-Distributed Vector Processing
@@ -905,6 +902,10 @@ definitely compelling enough to warrant in-depth investigation.
 
 **Use-case: Matrix and Convolutions**
 
+DRAFT image:
+
+<img src="https://ftp.libre-soc.org/20220614_122128.jpg" width=600 />
+
 First, some important definitions, because there are two different
 Vectorisation Modes in SVP64:
 
-- 
2.30.2