From 4669b4b1cab2945c1f4c6f08adf1045db8513bc8 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 25 Jan 2024 17:28:05 +0000 Subject: [PATCH] bug 1034: add crbinlog and crternlogi, rename crbinlog to crfbinlog --- openpower/isa/bitmanip.mdwn | 37 +++++++- openpower/isatables/RM-1P-2S1D.csv | 5 +- openpower/isatables/fields.text | 7 +- openpower/isatables/minor_22.csv | 3 +- openpower/isatables/minor_5.csv | 2 +- src/openpower/decoder/isa/caller.py | 3 +- src/openpower/decoder/power_decoder2.py | 7 ++ src/openpower/decoder/power_enums.py | 7 +- src/openpower/decoder/power_svp64.py | 11 ++- src/openpower/insndb/asm.py | 7 +- src/openpower/sv/sv_analysis.py | 6 +- src/openpower/test/bitmanip/bitmanip_cases.py | 90 +++++++++++-------- 12 files changed, 133 insertions(+), 52 deletions(-) diff --git a/openpower/isa/bitmanip.mdwn b/openpower/isa/bitmanip.mdwn index 0c2d735e..ae11d534 100644 --- a/openpower/isa/bitmanip.mdwn +++ b/openpower/isa/bitmanip.mdwn @@ -75,7 +75,7 @@ Special registers altered: CRB-Form -* crternlogi BF,BFA,BFB,TLI,msk +* crfternlogi BF,BFA,BFB,TLI,msk Pseudo-code: @@ -95,11 +95,26 @@ Special Registers Altered: CR field BF +# Condition Register Field Ternary Bitwise Logic Immediate + +CRB-Form + +* crternlogi BT,BA,BB,TLI + +Pseudo-code: + + idx <- CR[BT+32] || CR[BA+32] || CR[BB+32] + CR[4*BF+32] <- TLI[7-idx] + +Special Registers Altered: + + CR field BF + # Condition Register Field Dynamic Binary Logic CRB-Form -* crbinlog BF,BFA,BFB,msk +* crfbinlog BF,BFA,BFB,msk Pseudo-code: @@ -134,6 +149,24 @@ Special registers altered: CR field BF +# Condition Register Dynamic Binary Logic + +X-Form + +* crbinlog BT,BA,BFB + +Pseudo-code: + + a <- CR[BT+32] + b <- CR[BA] + lut <- CR[4*BFB+32:4*BFB+35] + idx <- CR[BT+32] || CR[BA+32] + CR[BT+32] <- lut[3-idx] + +Special registers altered: + + CR[BT+32] + # Add With Shift By Immediate Z23-Form diff --git a/openpower/isatables/RM-1P-2S1D.csv b/openpower/isatables/RM-1P-2S1D.csv index 79f1952a..bd27cc29 100644 --- a/openpower/isatables/RM-1P-2S1D.csv +++ b/openpower/isatables/RM-1P-2S1D.csv @@ -7,8 +7,9 @@ crand,CROP,,1P,EXTRA3,NO,d:BT,s:BA,s:BB,0,0,0,0,0,BA_BB,BT,0 creqv,CROP,,1P,EXTRA3,NO,d:BT,s:BA,s:BB,0,0,0,0,0,BA_BB,BT,0 crorc,CROP,,1P,EXTRA3,NO,d:BT,s:BA,s:BB,0,0,0,0,0,BA_BB,BT,0 cror,CROP,,1P,EXTRA3,NO,d:BT,s:BA,s:BB,0,0,0,0,0,BA_BB,BT,0 -crbinlog,CROP,,1P,EXTRA3,NO,d:BF,s:BFA,s:BFB,0,0,0,0,0,BFA_BFB_BF,BF,0 -crternlogi,CROP,,1P,EXTRA3,NO,d:BF,s:BFA,s:BFB,0,0,0,0,0,BFA_BFB_BF,BF,0 +crfbinlog,CROP,,1P,EXTRA3,NO,d:BF,s:BFA,s:BFB,0,0,0,0,0,BFA_BFB_BF,BF,0 +crbinlog,CROP,,1P,EXTRA3,NO,d:BT,s:BA,s:BFB,0,0,0,0,0,BA_BFB,BT,0 +crfternlogi,CROP,,1P,EXTRA3,NO,d:BF,s:BFA,s:BFB,0,0,0,0,0,BFA_BFB_BF,BF,0 cmp,CROP,,1P,EXTRA3,NO,d:BF,s:RA,s:RB,0,RA,RB,0,0,0,BF,0 cmpl,CROP,,1P,EXTRA3,NO,d:BF,s:RA,s:RB,0,RA,RB,0,0,0,BF,0 cmprb,CROP,,1P,EXTRA3,NO,d:BF,s:RA,s:RB,0,RA,RB,0,0,0,BF,0 diff --git a/openpower/isatables/fields.text b/openpower/isatables/fields.text index a36e42f4..b5b263e8 100644 --- a/openpower/isatables/fields.text +++ b/openpower/isatables/fields.text @@ -120,6 +120,7 @@ | PO | FRS | RA | RB | XO | / | | PO | FRSp | RA | RB | XO | / | | PO | BT | /// | /// | XO |Rc | + | PO | BT | BA | BFB // | XO | 1 | | PO | /// | RA | RB | XO | / | | PO | /// | /// | RB | XO | / | | PO | /// | /// | /// | XO | / | @@ -385,7 +386,7 @@ BA (11:15) Field used to specify a bit in the CR to be used as a source. - Formats: XL + Formats: XL, X BB (16:20) Field used to specify a bit in the CR to be used as a source. @@ -419,7 +420,7 @@ BFB (16:18) Field used to specify one of the CR fields to be used as a source. - Formats: CRB + Formats: CRB, X BH (19:20) Field used to specify a hint in the Branch Condi- tional to Link Register and Branch Conditional to @@ -446,7 +447,7 @@ BT (6:10) Field used to specify a bit in the CR or in the FPSCR to be used as a target. - Formats: XL + Formats: XL, X BX,B (30,16:20) Fields that are concatenated to specify a VSR to be used as a source. diff --git a/openpower/isatables/minor_22.csv b/openpower/isatables/minor_22.csv index 3f058868..b8faabc3 100644 --- a/openpower/isatables/minor_22.csv +++ b/openpower/isatables/minor_22.csv @@ -42,5 +42,6 @@ opcode,unit,internal op,in1,in2,in3,out,CR in,CR out,inv A,inv out,cry in,cry ou -----01011-,ALU,OP_FISHMV,FRS,CONST_UI,NONE,FRS,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,fishmv,DX,,1,unofficial until submitted and approved/renumbered by the opf isa wg 0101110110-,ALU,OP_BMAT,RA,NONE,NONE,RT,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,gbbd,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg ------00001,SHIFT_ROT,OP_BINLOG,RA,RB,RC,RT,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,binlog,BM2,,1,unofficial until submitted and approved/renumbered by the opf isa wg ------001001,CR,OP_CRBINLOG,NONE,NONE,NONE,NONE,BFA_BFB_BF,BF,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,crbinlog,CRB,,1,unofficial until submitted and approved/renumbered by the opf isa wg +-----001001,CR,OP_CRFBINLOG,NONE,NONE,NONE,NONE,BFA_BFB_BF,BF,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,crfbinlog,CRB,,1,unofficial until submitted and approved/renumbered by the opf isa wg +00001011101,CR,OP_CRBINLOG,NONE,NONE,NONE,NONE,BA_BFB,BT,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,crbinlog,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg diff --git a/openpower/isatables/minor_5.csv b/openpower/isatables/minor_5.csv index 80f575ed..bb110567 100644 --- a/openpower/isatables/minor_5.csv +++ b/openpower/isatables/minor_5.csv @@ -1,6 +1,6 @@ opcode,unit,internal op,in1,in2,in3,out,CR in,CR out,inv A,inv out,cry in,cry out,ldst len,BR,sgn ext,upd,rsrv,32b,sgn,rc,lk,sgl pipe,comment,form,CONDITIONS,unofficial,comment2 --------00-,SHIFT_ROT,OP_TERNLOG,RA,RB,RT,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,ternlogi,TLI,,1,unofficial until submitted and approved/renumbered by the opf isa wg ---------01-,CR,OP_CRTERNLOG,NONE,NONE,NONE,NONE,BFA_BFB_BF,BF,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,crternlogi,CRB,,1,unofficial until submitted and approved/renumbered by the opf isa wg +--------010,CR,OP_CRFTERNLOG,NONE,NONE,NONE,NONE,BFA_BFB_BF,BF,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,crfternlogi,CRB,,1,unofficial until submitted and approved/renumbered by the opf isa wg ------00100,ALU,OP_MADDSUBRS,RA,CONST_SH,RB,RT,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,1,0,NONE,0,0,maddsubrs,A,,1,unofficial until submitted and approved/renumbered by the opf isa wg ------01100,ALU,OP_MADDRS,RA,CONST_SH,RB,RT,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,1,0,NONE,0,0,maddrs,A,,1,unofficial until submitted and approved/renumbered by the opf isa wg ------10100,ALU,OP_MSUBRS,RA,CONST_SH,RB,RT,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,1,0,NONE,0,0,msubrs,A,,1,unofficial until submitted and approved/renumbered by the opf isa wg diff --git a/src/openpower/decoder/isa/caller.py b/src/openpower/decoder/isa/caller.py index b72a9eff..2544c61a 100644 --- a/src/openpower/decoder/isa/caller.py +++ b/src/openpower/decoder/isa/caller.py @@ -2275,7 +2275,8 @@ class ISACaller(ISACallerHelper, ISAFPHelpers, StepLoop): "brh", "brw", "brd", 'setvl', 'svindex', 'svremap', 'svstep', 'svshape', 'svshape2', - 'binlog', 'crbinlog', 'crternlogi', 'ternlogi', + 'binlog', 'crbinlog', 'crfbinlog', + 'crternlogi', 'crfternlogi', 'ternlogi', 'bmask', 'cprop', 'gbbd', 'absdu', 'absds', 'absdacs', 'absdacu', 'avgadd', 'fmvis', 'fishmv', 'pcdec', "maddedu", "divmod2du", diff --git a/src/openpower/decoder/power_decoder2.py b/src/openpower/decoder/power_decoder2.py index 9e3bca4a..51a2e334 100644 --- a/src/openpower/decoder/power_decoder2.py +++ b/src/openpower/decoder/power_decoder2.py @@ -661,6 +661,13 @@ class DecodeCRIn(Elaboratable): comb += self.cr_bitfield_b.ok.eq(1) comb += self.cr_bitfield_o.data.eq(self.dec.FormCRB.BF) comb += self.cr_bitfield_o.ok.eq(1) + with m.Case(CRInSel.BA_BFB): + comb += self.cr_bitfield.data.eq(self.dec.BA[2:5]) + comb += self.cr_bitfield.ok.eq(1) + comb += self.cr_bitfield_b.data.eq(self.dec.FormCRB.BFB) + comb += self.cr_bitfield_b.ok.eq(1) + comb += self.cr_bitfield_o.data.eq(self.dec.FormCRB.BF) + comb += self.cr_bitfield_o.ok.eq(1) with m.Case(CRInSel.BC): comb += self.cr_bitfield.data.eq(self.dec.BC[2:5]) comb += self.cr_bitfield.ok.eq(1) diff --git a/src/openpower/decoder/power_enums.py b/src/openpower/decoder/power_enums.py index 7d5ce4af..28c20189 100644 --- a/src/openpower/decoder/power_enums.py +++ b/src/openpower/decoder/power_enums.py @@ -749,8 +749,8 @@ _insns = [ "cprop", # AV bitmanip "crand", "crandc", "creqv", "crnand", "crnor", "cror", "crorc", "crxor", - "crbinlog", # binary bitmanip - "crternlogi", # ternary bitmanip + "crbinlog", "crfbinlog", # binary bitmanip (field and CR bit) + "crternlogi", "crfternlogi", # ternary bitmanip (field and CR bit) "darn", "dcbf", "dcbst", "dcbt", "dcbtst", "dcbz", "divd", "divde", "divdeo", "divdeu", @@ -972,6 +972,8 @@ class MicrOp(Enum): OP_CRTERNLOG = 113 OP_BINLOG = 114 OP_CRBINLOG = 115 + OP_CRFBINLOG = 116 + OP_CRFTERNLOG = 117 class SelType(Enum): @@ -1146,6 +1148,7 @@ class CRInSel(Enum): CR1 = 7 BA = 8 BFA_BFB_BF = 9 + BA_BFB = 10 # maaamma miiia... definitely time for CRin1/2 in CSV... def __str__(self): return self.name diff --git a/src/openpower/decoder/power_svp64.py b/src/openpower/decoder/power_svp64.py index cfa33805..9a635f8a 100644 --- a/src/openpower/decoder/power_svp64.py +++ b/src/openpower/decoder/power_svp64.py @@ -160,8 +160,15 @@ class SVP64RM: # BF is marked as a dest but is actually also src index1 = svp64_src.get('BFA', None) index2 = svp64_src.get('BFB', None) - index3 = svp64_dest.get('BF', None) # read-modify-write - entry['sv_cr_in'] = "Idx_%d_%d_%d" % (index1, index2, index3) + # long story, a kludge should allow the 3rd source to be id'd + #index3 = svp64_dest.get('BF', None) # read-modify-write + entry['sv_cr_in'] = "Idx_%d_%d" % (index1, index2) + elif cr_in == 'BA_BFB': + # three indices, BT and BA are 5-bit source, BFB is 3-bit + # BF is marked as a dest but is actually also src + index1 = svp64_src.get('BA', None) + index2 = svp64_src.get('BFB', None) + entry['sv_cr_in'] = "Idx_%d_%d" % (index1, index2) # CRout a lot easier. ignore WHOLE_REG for now cr_out = entry['CR out'] diff --git a/src/openpower/insndb/asm.py b/src/openpower/insndb/asm.py index 0d7f8c06..8f6ad336 100644 --- a/src/openpower/insndb/asm.py +++ b/src/openpower/insndb/asm.py @@ -85,6 +85,7 @@ class SVP64Asm: # identify if it is a word instruction record = DB[opcode] + #log("record", record) if record is not None: insn = WordInstruction.assemble(record=record, arguments=fields) yield from insn.disassemble(record=record, style=Style.LEGACY) @@ -101,6 +102,7 @@ class SVP64Asm: v30b_op = opmodes.pop(0) # first is the v3.0B record = DB[v30b_op] + #log("record v30b", record) if record is not None: insn = SVP64Instruction.assemble(record=record, arguments=fields, specifiers=opmodes) @@ -309,8 +311,9 @@ if __name__ == '__main__': ] lst = [ #"sv.cmp/ff=gt *0,*1,*2,0", - "dsld 5,4,5,3", - + #"dsld 5,4,5,3", + "crfbinlog 3,4,5,15", + #"crbinlog 3,4,5", ] isa = SVP64Asm(lst, macros=macros) log("list:\n", "\n\t".join(list(isa))) diff --git a/src/openpower/sv/sv_analysis.py b/src/openpower/sv/sv_analysis.py index b0e2ae4a..cc011e0a 100644 --- a/src/openpower/sv/sv_analysis.py +++ b/src/openpower/sv/sv_analysis.py @@ -546,10 +546,14 @@ def extra_classifier(insn_name, value, name, res, regs): elif value == 'RM-1P-2S1D': res['Etype'] = 'EXTRA3' # RM EXTRA3 type - if insn_name in ['crbinlog', 'crternlogi']: + if insn_name in ['crfbinlog', 'crfternlogi']: res['0'] = 'd:BF' # BF: Rdest1_EXTRA3 res['1'] = 's:BFA' # BFA: Rsrc1_EXTRA3 res['2'] = 's:BFB' # BFB: Rsrc2_EXTRA3 + elif insn_name == 'crbinlog': + res['0'] = 'd:BT' # BT: Rdest1_EXTRA3 + res['1'] = 's:BA' # BA: Rsrc1_EXTRA3 + res['2'] = 's:BFB' # BFB: Rsrc2_EXTRA3 elif insn_name.startswith('cr'): res['0'] = 'd:BT' # BT: Rdest1_EXTRA3 res['1'] = 's:BA' # BA: Rsrc1_EXTRA3 diff --git a/src/openpower/test/bitmanip/bitmanip_cases.py b/src/openpower/test/bitmanip/bitmanip_cases.py index a84bd2fb..eacdfeb8 100644 --- a/src/openpower/test/bitmanip/bitmanip_cases.py +++ b/src/openpower/test/bitmanip/bitmanip_cases.py @@ -18,6 +18,36 @@ def bmatflip(ra): return result +def crfbinlog(bf, bfa, bfb, mask): + lut = bfb + expected = bf&~mask # start at BF, mask overwrites masked bits only + checks = (bfa, bf) # LUT positions 1<<0=bfa 1<<1=bf + for i in range(4): + lut_index = 0 + for j, check in enumerate(checks): + if check & (1<> i) & 0b1 + if (lut & (1<> i) & 0b1 - if (lut & (1<