From 466bf764cd75ba1fd4f5f5b56083d6d10768750e Mon Sep 17 00:00:00 2001 From: lkcl Date: Thu, 5 May 2022 20:14:22 +0100 Subject: [PATCH] --- openpower/sv/SimpleV_rationale.mdwn | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) diff --git a/openpower/sv/SimpleV_rationale.mdwn b/openpower/sv/SimpleV_rationale.mdwn index bacaf933c..2fac410d7 100644 --- a/openpower/sv/SimpleV_rationale.mdwn +++ b/openpower/sv/SimpleV_rationale.mdwn @@ -254,7 +254,22 @@ of: * Defining the format of the prefix * Adding a `setvl` instruction -* Adding SPRs and working out how to do context-switches +* Adding Vector-context SPRs and working out how to do + context-switches with them * Writing an awful lot of Specification Documentation (4 years and counting) +Once the basics of this concept have sunk in, advancements quickly +follow: + +* Predication (an absolutely critical component for a Vector ISA). +* Element-width overrides: most Scalar ISAs today are 64-bit only, + with primarily Load and Store being able to handle 8/16/32/64 + and sometimes 128-bit (quad-word), where Vector ISAs need to + go as low as 8-bit arithmetic, even 8-bit Floating-Point for + high-performance AI. +* "Reordering" of the assumption of linear sequential element + access, for Matrices, rotations, transposition, Convolutions, + DCT, FFT, Parallel Prefix-Sum and other common transformations + that require significant effort in other ISAs. + -- 2.30.2