From 4676033d9f307aaee1e25dad4f8915aca8c1987d Mon Sep 17 00:00:00 2001
From: lkcl <lkcl@web>
Date: Sun, 24 May 2020 16:09:04 +0100
Subject: [PATCH]

---
 3d_gpu/architecture/regfile.mdwn | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/3d_gpu/architecture/regfile.mdwn b/3d_gpu/architecture/regfile.mdwn
index 674b406a6..551d54a16 100644
--- a/3d_gpu/architecture/regfile.mdwn
+++ b/3d_gpu/architecture/regfile.mdwn
@@ -7,6 +7,10 @@ A minimum of 3 register files are required for POWER:
 * Control and Condition Code Registers (CR0-7, CTR, LR)
 * SPRs (Special Purpose Registers)
 
+Source code:
+
+* <https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/regfile/regfiles.py;hb=HEAD>
+
 For a GPU, the FP and Integer registers need to be a massive 128 x 64-bit.
 
 # Regfile groups, Port Allocations and bit-widths
-- 
2.30.2