From 468780c045da1222290bde69496852d5d3ee6e43 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Tue, 30 Oct 2018 10:19:21 +0100 Subject: [PATCH] soc/cores/spi_flash: add endianness parameter --- litex/soc/cores/spi_flash.py | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --git a/litex/soc/cores/spi_flash.py b/litex/soc/cores/spi_flash.py index 4447e9f9..86cab3ee 100644 --- a/litex/soc/cores/spi_flash.py +++ b/litex/soc/cores/spi_flash.py @@ -1,6 +1,8 @@ from migen import * from migen.genlib.misc import timeline +from litex.gen import * + from litex.soc.interconnect import wishbone from litex.soc.interconnect.csr import AutoCSR, CSRStorage, CSRStatus @@ -26,7 +28,7 @@ def _format_cmd(cmd, spi_width): class SpiFlashDualQuad(Module, AutoCSR): - def __init__(self, pads, dummy=15, div=2): + def __init__(self, pads, dummy=15, div=2, endianness="big"): """ Simple SPI flash. Supports multi-bit pseudo-parallel reads (aka Dual or Quad I/O Fast @@ -56,7 +58,10 @@ class SpiFlashDualQuad(Module, AutoCSR): self.specials.dq = dq.get_tristate(pads.dq) sr = Signal(max(cmd_width, addr_width, wbone_width)) - self.comb += bus.dat_r.eq(sr) + if endianness == "big": + self.comb += bus.dat_r.eq(sr) + else: + self.comb += bus.dat_r.eq(reverse_bytes(sr)) self.comb += [ pads.clk.eq(clk), @@ -136,7 +141,10 @@ class SpiFlashSingle(Module, AutoCSR): addr_width = 24 sr = Signal(max(cmd_width, addr_width, wbone_width)) - self.comb += bus.dat_r.eq(sr) + if endianness == "big": + self.comb += bus.dat_r.eq(sr) + else: + self.comb += bus.dat_r.eq(reverse_bytes(sr)) self.comb += [ pads.clk.eq(clk), -- 2.30.2