From 468e7f1e5a404356776fb1303990f1284954b66c Mon Sep 17 00:00:00 2001 From: lkcl Date: Wed, 1 Sep 2021 20:11:40 +0100 Subject: [PATCH] --- openpower/sv/ldst.mdwn | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/openpower/sv/ldst.mdwn b/openpower/sv/ldst.mdwn index 31d100c96..51dafd692 100644 --- a/openpower/sv/ldst.mdwn +++ b/openpower/sv/ldst.mdwn @@ -222,7 +222,8 @@ Vector Indexed Mode, when elwidth overrides are applied. The source override applies to RB, and before adding to RA in order to calculate the Effective Address, if SEA is set RB is sign-extended from elwidth bits to the full 64 -bits. +bits. For other Modes (ffirst, saturate), +all EA computation is unsigned. Note that cache-inhibited LD/ST (`ldcix`) when VSPLAT is activated will perform **multiple** LD/ST operations, sequentially. `ldcix` even with scalar src will read the same memory location *multiple times*, storing the result in successive Vector destination registers. This because the cache-inhibit instructions are used to read and write memory-mapped peripherals. If a genuine cache-inhibited LD-VSPLAT is required then a *scalar* -- 2.30.2