From 46a3ea06be389f94db69e7a2ba67033b59c8d333 Mon Sep 17 00:00:00 2001 From: Matt Turner Date: Mon, 17 Oct 2016 14:12:28 -0700 Subject: [PATCH] i965/fs: Print the scheduler mode. Line wrap some awfully long lines while we are here. Reviewed-by: Kenneth Graunke Reviewed-by: Matt Turner Reviewed-by: Ian Romanick --- src/intel/compiler/brw_fs.cpp | 7 +++++++ src/intel/compiler/brw_fs.h | 1 + src/intel/compiler/brw_fs_generator.cpp | 27 +++++++++++++++++-------- src/intel/compiler/brw_fs_visitor.cpp | 1 + 4 files changed, 28 insertions(+), 8 deletions(-) diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp index c5d30a0e7ed..89a6a7f6974 100644 --- a/src/intel/compiler/brw_fs.cpp +++ b/src/intel/compiler/brw_fs.cpp @@ -7213,6 +7213,12 @@ fs_visitor::allocate_registers(unsigned min_dispatch_width, bool allow_spilling) SCHEDULE_PRE_LIFO, }; + static const char *scheduler_mode_name[] = { + "top-down", + "non-lifo", + "lifo" + }; + bool spill_all = allow_spilling && (INTEL_DEBUG & DEBUG_SPILL_FS); /* Try each scheduling heuristic to see if it can successfully register @@ -7221,6 +7227,7 @@ fs_visitor::allocate_registers(unsigned min_dispatch_width, bool allow_spilling) */ for (unsigned i = 0; i < ARRAY_SIZE(pre_modes); i++) { schedule_instructions(pre_modes[i]); + this->shader_stats.scheduler_mode = scheduler_mode_name[i]; if (0) { assign_regs_trivial(); diff --git a/src/intel/compiler/brw_fs.h b/src/intel/compiler/brw_fs.h index 8aa3d3482c9..020d42356eb 100644 --- a/src/intel/compiler/brw_fs.h +++ b/src/intel/compiler/brw_fs.h @@ -53,6 +53,7 @@ offset(const fs_reg ®, const brw::fs_builder &bld, unsigned delta) #define UBO_START ((1 << 16) - 4) struct shader_stats { + const char *scheduler_mode; unsigned promoted_constants; }; diff --git a/src/intel/compiler/brw_fs_generator.cpp b/src/intel/compiler/brw_fs_generator.cpp index d9abf9a0153..14cfdd77641 100644 --- a/src/intel/compiler/brw_fs_generator.cpp +++ b/src/intel/compiler/brw_fs_generator.cpp @@ -2250,10 +2250,17 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width) if (unlikely(debug_flag)) { fprintf(stderr, "Native code for %s\n" - "SIMD%d shader: %d instructions. %d loops. %u cycles. %d:%d spills:fills. Promoted %u constants. Compacted %d to %d" - " bytes (%.0f%%)\n", - shader_name, dispatch_width, before_size / 16, loop_count, cfg->cycle_count, - spill_count, fill_count, shader_stats.promoted_constants, before_size, after_size, + "SIMD%d shader: %d instructions. %d loops. %u cycles. " + "%d:%d spills:fills. " + "scheduled with mode %s. " + "Promoted %u constants. " + "Compacted %d to %d bytes (%.0f%%)\n", + shader_name, dispatch_width, before_size / 16, + loop_count, cfg->cycle_count, + spill_count, fill_count, + shader_stats.scheduler_mode, + shader_stats.promoted_constants, + before_size, after_size, 100.0f * (before_size - after_size) / before_size); dump_assembly(p->store, disasm_info); @@ -2263,13 +2270,17 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width) compiler->shader_debug_log(log_data, "%s SIMD%d shader: %d inst, %d loops, %u cycles, " - "%d:%d spills:fills, Promoted %u constants, " + "%d:%d spills:fills, " + "scheduled with mode %s, " + "Promoted %u constants, " "compacted %d to %d bytes.", _mesa_shader_stage_to_abbrev(stage), dispatch_width, before_size / 16, - loop_count, cfg->cycle_count, spill_count, - fill_count, shader_stats.promoted_constants, before_size, - after_size); + loop_count, cfg->cycle_count, + spill_count, fill_count, + shader_stats.scheduler_mode, + shader_stats.promoted_constants, + before_size, after_size); return start_offset; } diff --git a/src/intel/compiler/brw_fs_visitor.cpp b/src/intel/compiler/brw_fs_visitor.cpp index 72e94beaf17..273433f3e5e 100644 --- a/src/intel/compiler/brw_fs_visitor.cpp +++ b/src/intel/compiler/brw_fs_visitor.cpp @@ -952,6 +952,7 @@ fs_visitor::init() this->pull_constant_loc = NULL; this->push_constant_loc = NULL; + this->shader_stats.scheduler_mode = NULL; this->shader_stats.promoted_constants = 0, this->grf_used = 0; -- 2.30.2