From 46af9a0ff7727c2d47b1dc12501e3328cba1f2e9 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 18 Oct 2019 09:06:43 +0200 Subject: [PATCH] hierarchy - proc reorder --- tests/anlogic/add_sub.ys | 1 + tests/anlogic/dffs.ys | 4 ++-- tests/anlogic/latches.ys | 6 +++--- tests/anlogic/mux.ys | 8 ++++---- 4 files changed, 10 insertions(+), 9 deletions(-) diff --git a/tests/anlogic/add_sub.ys b/tests/anlogic/add_sub.ys index 994cd0d03..b8b67cc46 100644 --- a/tests/anlogic/add_sub.ys +++ b/tests/anlogic/add_sub.ys @@ -1,5 +1,6 @@ read_verilog add_sub.v hierarchy -top top +proc equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module diff --git a/tests/anlogic/dffs.ys b/tests/anlogic/dffs.ys index 38dffa326..9cbe5fce7 100644 --- a/tests/anlogic/dffs.ys +++ b/tests/anlogic/dffs.ys @@ -1,8 +1,8 @@ read_verilog dffs.v design -save read -proc hierarchy -top dff +proc equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd dff # Constrain all select calls below inside the top module @@ -10,8 +10,8 @@ select -assert-count 1 t:AL_MAP_SEQ select -assert-none t:AL_MAP_SEQ %% t:* %D design -load read -proc hierarchy -top dffe +proc equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd dffe # Constrain all select calls below inside the top module diff --git a/tests/anlogic/latches.ys b/tests/anlogic/latches.ys index ae9e15ff8..c00c7a25d 100644 --- a/tests/anlogic/latches.ys +++ b/tests/anlogic/latches.ys @@ -1,8 +1,8 @@ read_verilog latches.v design -save read -proc hierarchy -top latchp +proc # Can't run any sort of equivalence check because latches are blown to LUTs synth_anlogic cd latchp # Constrain all select calls below inside the top module @@ -12,8 +12,8 @@ select -assert-none t:AL_MAP_LUT3 %% t:* %D design -load read -proc hierarchy -top latchn +proc # Can't run any sort of equivalence check because latches are blown to LUTs synth_anlogic cd latchn # Constrain all select calls below inside the top module @@ -23,8 +23,8 @@ select -assert-none t:AL_MAP_LUT3 %% t:* %D design -load read -proc hierarchy -top latchsr +proc # Can't run any sort of equivalence check because latches are blown to LUTs synth_anlogic cd latchsr # Constrain all select calls below inside the top module diff --git a/tests/anlogic/mux.ys b/tests/anlogic/mux.ys index 354fc836c..64ed2a2bd 100644 --- a/tests/anlogic/mux.ys +++ b/tests/anlogic/mux.ys @@ -1,8 +1,8 @@ read_verilog mux.v design -save read -proc hierarchy -top mux2 +proc equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux2 # Constrain all select calls below inside the top module @@ -11,8 +11,8 @@ select -assert-count 1 t:AL_MAP_LUT3 select -assert-none t:AL_MAP_LUT3 %% t:* %D design -load read -proc hierarchy -top mux4 +proc equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux4 # Constrain all select calls below inside the top module @@ -21,8 +21,8 @@ select -assert-count 1 t:AL_MAP_LUT6 select -assert-none t:AL_MAP_LUT6 %% t:* %D design -load read -proc hierarchy -top mux8 +proc equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux8 # Constrain all select calls below inside the top module @@ -32,8 +32,8 @@ select -assert-count 1 t:AL_MAP_LUT6 select -assert-none t:AL_MAP_LUT4 t:AL_MAP_LUT6 %% t:* %D design -load read -proc hierarchy -top mux16 +proc equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux16 # Constrain all select calls below inside the top module -- 2.30.2