From 46d5ea6bfaf65405a314b8787e39ef3ca8a205d6 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sat, 24 Nov 2018 03:54:33 +0000 Subject: [PATCH] clarify modes on LD/ST --- simple_v_extension/specification.mdwn | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/simple_v_extension/specification.mdwn b/simple_v_extension/specification.mdwn index b5392e716..d519e8a85 100644 --- a/simple_v_extension/specification.mdwn +++ b/simple_v_extension/specification.mdwn @@ -1267,11 +1267,11 @@ for LOAD/STORE: * Read (or write for STORE) from sequential locations, where one register specifies the address, and the one address is incremented - by a fixed amount. + by a fixed amount. This is usually known as "Unit Stride" mode. * Read (or write) from multiple indirected addresses, where the vector elements each specify separate and distinct addresses. -To support these different addressing modes, the CSR "isvector" +To support these different addressing modes, the CSR Register "isvector" bit is used. So, for a LOAD, when the src register is set to scalar, the LOADs are sequentially incremented by the src register element width, and when the src register is set to "vector", the @@ -1287,8 +1287,10 @@ pseudo-code would look like this: if (int_csr[rs].isvec) while (!(ps & 1<