From 46e611175ec6d8a0383c64c1564e956df02fa7b2 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sun, 5 Jul 2020 15:16:13 +0100 Subject: [PATCH] sigh read and write xer detection, fix spr and trap compunit tests --- src/soc/decoder/decode2execute1.py | 2 ++ src/soc/decoder/power_decoder2.py | 8 ++++++++ src/soc/decoder/power_regspec_map.py | 12 ++++++------ src/soc/fu/compunits/test/test_compunit.py | 2 ++ .../fu/compunits/test/test_spr_compunit.py | 2 +- .../fu/compunits/test/test_trap_compunit.py | 2 +- src/soc/fu/test/common.py | 19 +++++++++++++------ 7 files changed, 33 insertions(+), 14 deletions(-) diff --git a/src/soc/decoder/decode2execute1.py b/src/soc/decoder/decode2execute1.py index 75e29e1b..df98c0f4 100644 --- a/src/soc/decoder/decode2execute1.py +++ b/src/soc/decoder/decode2execute1.py @@ -58,6 +58,8 @@ class Decode2ToExecute1Type(RecordObject): self.lk = Signal(reset_less=True) self.rc = Data(1, "rc") self.oe = Data(1, "oe") + self.xer_in = Signal(reset_less=True) # xer might be read + self.xer_out = Signal(reset_less=True) # xer might be written self.invert_a = Signal(reset_less=True) self.zero_a = Signal(reset_less=True) self.invert_out = Signal(reset_less=True) diff --git a/src/soc/decoder/power_decoder2.py b/src/soc/decoder/power_decoder2.py index 5fd01058..125fef67 100644 --- a/src/soc/decoder/power_decoder2.py +++ b/src/soc/decoder/power_decoder2.py @@ -642,6 +642,14 @@ class PowerDecode2(Elaboratable): comb += e.input_cr.eq(op.cr_in) # condition reg comes in comb += e.output_cr.eq(op.cr_out) # condition reg goes in + # sigh this is exactly the sort of thing for which the + # decoder is designed to not need. MTSPR, MFSPR and others need + # access to the XER bits. however setting e.oe is not appropriate + with m.If(op.internal_op == InternalOp.OP_MFSPR): + comb += e.xer_in.eq(1) + with m.If(op.internal_op == InternalOp.OP_MTSPR): + comb += e.xer_out.eq(1) + # set the trapaddr to 0x700 for a td/tw/tdi/twi operation with m.If(op.internal_op == InternalOp.OP_TRAP): comb += e.trapaddr.eq(0x70) # addr=0x700 (strip first nibble) diff --git a/src/soc/decoder/power_regspec_map.py b/src/soc/decoder/power_regspec_map.py index 6f461c96..51a101de 100644 --- a/src/soc/decoder/power_regspec_map.py +++ b/src/soc/decoder/power_regspec_map.py @@ -68,11 +68,11 @@ def regspec_decode_read(e, regfile, name): CA = 1<