From 46f0932c4c61aca3ab5332f99a4a60d110b52191 Mon Sep 17 00:00:00 2001 From: Claire Xenia Wolf Date: Thu, 1 Oct 2020 18:26:53 +0200 Subject: [PATCH] Ignore empty parameters in Verilog module instantiations Fixes #2394 Signed-off-by: Claire Xenia Wolf --- frontends/verilog/verilog_parser.y | 3 +++ 1 file changed, 3 insertions(+) diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index 8e5236639..678ce6c87 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -1891,6 +1891,9 @@ cell_parameter: astbuf1->children.push_back(node); node->children.push_back($1); } | + '.' TOK_ID '(' ')' { + // just ignore empty parameters + } | '.' TOK_ID '(' expr ')' { AstNode *node = new AstNode(AST_PARASET); node->str = *$2; -- 2.30.2