From 471393d0f98a6b6fa631be72e1154e0bb0e5f8fd Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Wed, 1 May 2013 21:52:26 +0200 Subject: [PATCH] actorlib/dma_asmi: drive dat_wm --- migen/actorlib/dma_asmi.py | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/migen/actorlib/dma_asmi.py b/migen/actorlib/dma_asmi.py index c348c4f7..77f1b83a 100644 --- a/migen/actorlib/dma_asmi.py +++ b/migen/actorlib/dma_asmi.py @@ -89,7 +89,8 @@ class SequentialWriter(Module): port.adr.eq(self.address_data.payload.a), port.we.eq(1), port.stb.eq(self.address_data.stb), - self.address_data.ack.eq(port.ack) + self.address_data.ack.eq(port.ack), + port.dat_wm.eq(0) ] self.sync += [ port.dat_w.eq(0), @@ -112,7 +113,10 @@ class _WriteSlot(Module): drive_data = Signal() data_reg = Signal(port.hub.dw) - self.comb += If(drive_data, port.dat_w.eq(data_reg)) + self.comb += [ + If(drive_data, port.dat_w.eq(data_reg)), + port.dat_wm.eq(0) + ] self.sync += [ If(port.stb & port.ack & (port.tag_issue == (port.base + n)), -- 2.30.2