From 4715e7a98afbb43872ead144e35272f256549be0 Mon Sep 17 00:00:00 2001 From: Fritz Koenig Date: Mon, 7 Jan 2019 12:00:41 -0800 Subject: [PATCH] freedreno: UBWC allocator UBWC requires space for a metadata or flag buffer that contains compression data. Each 16x4 tile of image data corresponds to a byte of compression data. This buffer needs to be stored before (at a lower address) the image buffer in order to match up with what the display driver. This allows the display driver to directly scan-out at UBWC buffer. --- .../drivers/freedreno/a6xx/fd6_resource.c | 34 +++++++++++++++++++ .../drivers/freedreno/a6xx/fd6_resource.h | 1 + .../drivers/freedreno/a6xx/fd6_screen.c | 1 + 3 files changed, 36 insertions(+) diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_resource.c b/src/gallium/drivers/freedreno/a6xx/fd6_resource.c index ff869d7d87b..e15a7ba44bb 100644 --- a/src/gallium/drivers/freedreno/a6xx/fd6_resource.c +++ b/src/gallium/drivers/freedreno/a6xx/fd6_resource.c @@ -27,6 +27,8 @@ #include "fd6_resource.h" +#include "a6xx.xml.h" + /* indexed by cpp, including msaa 2x and 4x: */ static const struct { unsigned pitchalign; @@ -159,6 +161,38 @@ setup_slices(struct fd_resource *rsc, uint32_t alignment, enum pipe_format forma return size; } +uint32_t +fd6_fill_ubwc_buffer_sizes(struct fd_resource *rsc) +{ +#define RGB_TILE_WIDTH 16 +#define RBG_TILE_WIDTH_ALIGNMENT 64 +#define RGB_TILE_HEIGHT 4 +#define RGB_TILE_HEIGHT_ALIGNMENT 16 +#define UBWC_PLANE_SIZE_ALIGNMENT 4096 + + struct pipe_resource *prsc = &rsc->base; + uint32_t width = prsc->width0; + uint32_t height = prsc->height0; + + /* limit things to simple single level 2d for now: */ + if ((prsc->depth0 != 1) || (prsc->array_size != 1) || (prsc->last_level != 0)) + return 0; + + uint32_t meta_stride = + ALIGN_POT(DIV_ROUND_UP(width, RGB_TILE_WIDTH), RBG_TILE_WIDTH_ALIGNMENT); + uint32_t meta_scanlines = + ALIGN_POT(DIV_ROUND_UP(height, RGB_TILE_HEIGHT), RGB_TILE_HEIGHT_ALIGNMENT); + uint32_t meta_plane = + ALIGN_POT(meta_stride * meta_scanlines, UBWC_PLANE_SIZE_ALIGNMENT); + + rsc->offset = meta_plane; + rsc->ubwc_pitch = meta_stride; + rsc->ubwc_size = meta_plane >> 2; + rsc->tile_mode = TILE6_3; + + return rsc->ubwc_size; +} + uint32_t fd6_setup_slices(struct fd_resource *rsc) { diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_resource.h b/src/gallium/drivers/freedreno/a6xx/fd6_resource.h index a19f2744dd7..83b6fb246c7 100644 --- a/src/gallium/drivers/freedreno/a6xx/fd6_resource.h +++ b/src/gallium/drivers/freedreno/a6xx/fd6_resource.h @@ -30,6 +30,7 @@ #include "freedreno_resource.h" +uint32_t fd6_fill_ubwc_buffer_sizes(struct fd_resource *rsc); uint32_t fd6_setup_slices(struct fd_resource *rsc); #endif /* FD6_RESOURCE_H_ */ diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_screen.c b/src/gallium/drivers/freedreno/a6xx/fd6_screen.c index be92d4a877b..d5c78c16dc7 100644 --- a/src/gallium/drivers/freedreno/a6xx/fd6_screen.c +++ b/src/gallium/drivers/freedreno/a6xx/fd6_screen.c @@ -136,4 +136,5 @@ fd6_screen_init(struct pipe_screen *pscreen) screen->setup_slices = fd6_setup_slices; screen->tile_mode = fd6_tile_mode; + screen->fill_ubwc_buffer_sizes = fd6_fill_ubwc_buffer_sizes; } -- 2.30.2