From 4715f6c72cc4c5d0e13bb4cac536eb1f31c313cb Mon Sep 17 00:00:00 2001
From: Giacomo Travaglini <giacomo.travaglini@arm.com>
Date: Tue, 28 Jul 2020 10:14:12 +0100
Subject: [PATCH] dev-arm: Make the Sp805 use the new ArmInterruptPin::active

Change-Id: I65b53b33e13345eca93a76e82efac7f8c0b97755
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31939
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
---
 src/dev/arm/watchdog_sp805.cc | 11 +++--------
 src/dev/arm/watchdog_sp805.hh |  3 ---
 2 files changed, 3 insertions(+), 11 deletions(-)

diff --git a/src/dev/arm/watchdog_sp805.cc b/src/dev/arm/watchdog_sp805.cc
index bed625866..3fd7006ae 100644
--- a/src/dev/arm/watchdog_sp805.cc
+++ b/src/dev/arm/watchdog_sp805.cc
@@ -49,7 +49,6 @@ Sp805::Sp805(Sp805Params const* params)
       persistedValue(timeoutInterval),
       enabled(false),
       resetEnabled(false),
-      intRaised(false),
       writeAccessEnabled(true),
       integrationTestEnabled(false),
       timeoutEvent([this] { timeoutExpired(); }, name())
@@ -78,10 +77,10 @@ Sp805::read(PacketPtr pkt)
         warn("Sp805::read: WO reg (0x%x) [WDOGINTCLR]\n", addr);
         break;
       case WDOGRIS:
-        resp = intRaised;
+        resp = interrupt->active();
         break;
       case WDOGMIS:
-        resp = intRaised & enabled;
+        resp = interrupt->active() && enabled;
         break;
       case WDOGLOCK:
         resp = writeAccessEnabled;
@@ -210,11 +209,10 @@ Sp805::sendInt()
 {
     // If the previously sent interrupt has not been served,
     // assert system reset if enabled
-    if (intRaised & enabled) {
+    if (interrupt->active() && enabled) {
         if (resetEnabled)
             warn("Watchdog timed out, system reset asserted\n");
     } else {
-        intRaised = true;
         interrupt->raise();
     }
 }
@@ -222,7 +220,6 @@ Sp805::sendInt()
 void
 Sp805::clearInt()
 {
-    intRaised = false;
     interrupt->clear();
 }
 
@@ -234,7 +231,6 @@ Sp805::serialize(CheckpointOut &cp) const
     SERIALIZE_SCALAR(persistedValue);
     SERIALIZE_SCALAR(enabled);
     SERIALIZE_SCALAR(resetEnabled);
-    SERIALIZE_SCALAR(intRaised);
     SERIALIZE_SCALAR(writeAccessEnabled);
     SERIALIZE_SCALAR(integrationTestEnabled);
 
@@ -252,7 +248,6 @@ Sp805::unserialize(CheckpointIn &cp)
     UNSERIALIZE_SCALAR(persistedValue);
     UNSERIALIZE_SCALAR(enabled);
     UNSERIALIZE_SCALAR(resetEnabled);
-    UNSERIALIZE_SCALAR(intRaised);
     UNSERIALIZE_SCALAR(writeAccessEnabled);
     UNSERIALIZE_SCALAR(integrationTestEnabled);
 
diff --git a/src/dev/arm/watchdog_sp805.hh b/src/dev/arm/watchdog_sp805.hh
index c2e99cd9c..4d9094d17 100644
--- a/src/dev/arm/watchdog_sp805.hh
+++ b/src/dev/arm/watchdog_sp805.hh
@@ -93,9 +93,6 @@ class Sp805 : public AmbaIntDevice
     /** Indicates if reset behaviour is enabled when counter reaches 0 */
     bool resetEnabled;
 
-    /** Indicates if an interrupt has been raised by the counter reaching 0 */
-    bool intRaised;
-
     /** Indicates if write access to registers is enabled */
     bool writeAccessEnabled;
 
-- 
2.30.2