From 473997df2693e7ad4b13e64aa234dbab83b4eb2d Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 2 Mar 2015 12:25:59 +0100 Subject: [PATCH] cpuif: add CSR_ prefix to CSR base addresses (avoid conflicts between CSR and mems bases) --- misoclib/mem/sdram/core/__init__.py | 3 --- misoclib/soc/cpuif.py | 4 ++-- software/bios/boot.c | 2 +- software/bios/main.c | 18 +++++++++--------- software/bios/sdram.c | 8 ++++---- software/bios/sdram.h | 2 +- software/include/hw/ethmac_mem.h | 8 ++++---- software/libbase/spiflash.c | 6 +++--- software/libbase/system.c | 2 +- software/libnet/microudp.c | 2 +- targets/kc705.py | 2 +- targets/mlabs_video.py | 2 +- 12 files changed, 28 insertions(+), 31 deletions(-) diff --git a/misoclib/mem/sdram/core/__init__.py b/misoclib/mem/sdram/core/__init__.py index c241b631..c4a5f9fb 100644 --- a/misoclib/mem/sdram/core/__init__.py +++ b/misoclib/mem/sdram/core/__init__.py @@ -21,9 +21,6 @@ class SDRAMCore(Module, AutoCSR): # MINICON elif ramcon_type == "minicon": - if self.with_l2: - raise ValueError("MINICON does not implement L2 cache (Use LASMICON or disable L2 cache (with_l2=False))") - self.submodules.controller = controller = minicon.Minicon(phy, sdram_geom, sdram_timing) self.comb += Record.connect(controller.dfi, self.dfii.slave) else: diff --git a/misoclib/soc/cpuif.py b/misoclib/soc/cpuif.py index 57d365b8..7bbe5ad1 100644 --- a/misoclib/soc/cpuif.py +++ b/misoclib/soc/cpuif.py @@ -73,10 +73,10 @@ def get_csr_header(regions, interrupt_map): for name, origin, busword, obj in regions: if isinstance(obj, Memory): fullname = name + "_" + memory.name_override - r += "#define "+fullname.upper()+"_BASE "+hex(origin)+"\n" + r += "#define CSR_"+fullname.upper()+"_BASE "+hex(origin)+"\n" else: r += "\n/* "+name+" */\n" - r += "#define "+name.upper()+"_BASE "+hex(origin)+"\n" + r += "#define CSR_"+name.upper()+"_BASE "+hex(origin)+"\n" for csr in obj: nr = (csr.size + busword - 1)//busword r += _get_rw_functions(name + "_" + csr.name, origin, nr, busword, isinstance(csr, CSRStatus)) diff --git a/software/bios/boot.c b/software/bios/boot.c index 1c5c14a8..210937e6 100644 --- a/software/bios/boot.c +++ b/software/bios/boot.c @@ -176,7 +176,7 @@ void serialboot(void) } } -#ifdef ETHMAC_BASE +#ifdef CSR_ETHMAC_BASE #define LOCALIP1 192 #define LOCALIP2 168 diff --git a/software/bios/main.c b/software/bios/main.c index fad8e4ef..5c92b93e 100644 --- a/software/bios/main.c +++ b/software/bios/main.c @@ -319,7 +319,7 @@ static void help(void) puts("rcsr - read processor CSR"); puts("wcsr - write processor CSR"); #endif -#ifdef ETHMAC_BASE +#ifdef CSR_ETHMAC_BASE puts("netboot - boot via TFTP"); #endif puts("serialboot - boot via SFL"); @@ -361,7 +361,7 @@ static void do_command(char *c) else if(strcmp(token, "flashboot") == 0) flashboot(); #endif else if(strcmp(token, "serialboot") == 0) serialboot(); -#ifdef ETHMAC_BASE +#ifdef CSR_ETHMAC_BASE else if(strcmp(token, "netboot") == 0) netboot(); #endif @@ -374,7 +374,7 @@ static void do_command(char *c) else if(strcmp(token, "wcsr") == 0) wcsr(get_token(&c), get_token(&c)); #endif -#ifdef SDRAM_BASE +#ifdef CSR_SDRAM_BASE else if(strcmp(token, "sdrrow") == 0) sdrrow(get_token(&c)); else if(strcmp(token, "sdrsw") == 0) sdrsw(); else if(strcmp(token, "sdrhw") == 0) sdrhw(); @@ -382,7 +382,7 @@ static void do_command(char *c) else if(strcmp(token, "sdrrd") == 0) sdrrd(get_token(&c), get_token(&c)); else if(strcmp(token, "sdrrderr") == 0) sdrrderr(get_token(&c)); else if(strcmp(token, "sdrwr") == 0) sdrwr(get_token(&c)); -#ifdef DDRPHY_BASE +#ifdef CSR_DDRPHY_BASE else if(strcmp(token, "sdrwlon") == 0) sdrwlon(); else if(strcmp(token, "sdrwloff") == 0) sdrwloff(); else if(strcmp(token, "sdrlevel") == 0) sdrlevel(); @@ -464,7 +464,7 @@ static int test_user_abort(void) printf("Automatic boot in 2 seconds...\n"); printf("Q/ESC: abort boot\n"); printf("F7: boot from serial\n"); -#ifdef ETHMAC_BASE +#ifdef CSR_ETHMAC_BASE printf("F8: boot from network\n"); #endif timer0_en_write(0); @@ -483,7 +483,7 @@ static int test_user_abort(void) serialboot(); return 0; } -#ifdef ETHMAC_BASE +#ifdef CSR_ETHMAC_BASE if(c == 0x07) { netboot(); return 0; @@ -502,7 +502,7 @@ static void boot_sequence(void) flashboot(); #endif serialboot(); -#ifdef ETHMAC_BASE +#ifdef CSR_ETHMAC_BASE netboot(); #endif printf("No boot medium found\n"); @@ -522,10 +522,10 @@ int main(int i, char **c) printf("Revision %08x built "__DATE__" "__TIME__"\n\n", MSC_GIT_ID); crcbios(); id_print(); -#ifdef ETHMAC_BASE +#ifdef CSR_ETHMAC_BASE ethreset(); #endif -#ifdef SDRAM_BASE +#ifdef CSR_SDRAM_BASE sdr_ok = sdrinit(); #else sdr_ok = 1; diff --git a/software/bios/sdram.c b/software/bios/sdram.c index 8e291763..785dcde3 100644 --- a/software/bios/sdram.c +++ b/software/bios/sdram.c @@ -1,5 +1,5 @@ #include -#ifdef SDRAM_BASE +#ifdef CSR_SDRAM_BASE #include #include @@ -191,7 +191,7 @@ void sdrwr(char *startaddr) command_pwr(DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS|DFII_COMMAND_WRDATA); } -#ifdef DDRPHY_BASE +#ifdef CSR_DDRPHY_BASE void sdrwlon(void) { @@ -420,7 +420,7 @@ int sdrlevel(void) return 1; } -#endif /* DDRPHY_BASE */ +#endif /* CSR_DDRPHY_BASE */ #define TEST_SIZE (2*1024*1024) @@ -475,7 +475,7 @@ int sdrinit(void) printf("Initializing SDRAM...\n"); init_sequence(); -#ifdef DDRPHY_BASE +#ifdef CSR_DDRPHY_BASE if(!sdrlevel()) return 0; #endif diff --git a/software/bios/sdram.h b/software/bios/sdram.h index aea70982..c5d0984f 100644 --- a/software/bios/sdram.h +++ b/software/bios/sdram.h @@ -11,7 +11,7 @@ void sdrrd(char *startaddr, char *dq); void sdrrderr(char *count); void sdrwr(char *startaddr); -#ifdef DDRPHY_BASE +#ifdef CSR_DDRPHY_BASE void sdrwlon(void); void sdrwloff(void); int sdrlevel(void); diff --git a/software/include/hw/ethmac_mem.h b/software/include/hw/ethmac_mem.h index c57e1751..03c7b96d 100644 --- a/software/include/hw/ethmac_mem.h +++ b/software/include/hw/ethmac_mem.h @@ -3,9 +3,9 @@ #include -#define ETHMAC_RX0_BASE ETHMAC_MEM_BASE -#define ETHMAC_RX1_BASE (ETHMAC_MEM_BASE+0x0800) -#define ETHMAC_TX0_BASE (ETHMAC_MEM_BASE+0x1000) -#define ETHMAC_TX1_BASE (ETHMAC_MEM_BASE+0x1800) +#define ETHMAC_RX0_BASE ETHMAC_BASE +#define ETHMAC_RX1_BASE (ETHMAC_BASE+0x0800) +#define ETHMAC_TX0_BASE (ETHMAC_BASE+0x1000) +#define ETHMAC_TX1_BASE (ETHMAC_BASE+0x1800) #endif diff --git a/software/libbase/spiflash.c b/software/libbase/spiflash.c index b57b7e98..b2080248 100644 --- a/software/libbase/spiflash.c +++ b/software/libbase/spiflash.c @@ -2,7 +2,7 @@ #include -#ifdef SPIFLASH_BASE +#ifdef CSR_SPIFLASH_BASE #define PAGE_PROGRAM_CMD (0x02) #define WRDI_CMD (0x04) @@ -33,7 +33,7 @@ static void flash_write_byte(unsigned char b) spiflash_bitbang_write(0); // ~CS_N ~CLK for(i = 0; i < 8; i++, b <<= 1) { - + spiflash_bitbang_write((b & 0x80) >> 7); spiflash_bitbang_write(((b & 0x80) >> 7) | BITBANG_CLK); } @@ -84,7 +84,7 @@ void erase_flash_sector(unsigned int addr) flash_write_byte(WREN_CMD); spiflash_bitbang_write(BITBANG_CS_N); - + flash_write_byte(SE_CMD); flash_write_addr(sector_addr); spiflash_bitbang_write(BITBANG_CS_N); diff --git a/software/libbase/system.c b/software/libbase/system.c index 4a71b206..ca618504 100644 --- a/software/libbase/system.c +++ b/software/libbase/system.c @@ -67,7 +67,7 @@ void flush_cpu_dcache(void) #endif } -#ifdef WISHBONE2LASMI_BASE +#ifdef CSR_WISHBONE2LASMI_BASE void flush_l2_cache(void) { unsigned int l2_nwords; diff --git a/software/libnet/microudp.c b/software/libnet/microudp.c index a8faa45d..fa69afe9 100644 --- a/software/libnet/microudp.c +++ b/software/libnet/microudp.c @@ -1,5 +1,5 @@ #include -#ifdef ETHMAC_BASE +#ifdef CSR_ETHMAC_BASE #include #include diff --git a/targets/kc705.py b/targets/kc705.py index e1007e9b..b3587466 100644 --- a/targets/kc705.py +++ b/targets/kc705.py @@ -134,6 +134,6 @@ class MiniSoC(BaseSoC): self.submodules.ethphy = LiteEthPHYGMII(platform.request("eth_clocks"), platform.request("eth")) self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone") self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus) - self.add_memory_region("ethmac_mem", self.mem_map["ethmac"]+0x80000000, 0x2000) + self.add_memory_region("ethmac", self.mem_map["ethmac"]+0x80000000, 0x2000) default_subtarget = BaseSoC diff --git a/targets/mlabs_video.py b/targets/mlabs_video.py index 8eafcdcc..c6e10c30 100644 --- a/targets/mlabs_video.py +++ b/targets/mlabs_video.py @@ -108,7 +108,7 @@ class MiniSoC(BaseSoC): self.submodules.ethphy = LiteEthPHYMII(platform.request("eth_clocks"), platform.request("eth")) self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone") self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus) - self.add_memory_region("ethmac_mem", self.mem_map["ethmac"]+0x80000000, 0x2000) + self.add_memory_region("ethmac", self.mem_map["ethmac"]+0x80000000, 0x2000) def get_vga_dvi(platform): try: -- 2.30.2