From 475fe500bfe495ffa0715e7a19d044b8d6f4f341 Mon Sep 17 00:00:00 2001 From: Brian Ho Date: Wed, 1 Apr 2020 13:26:17 -0700 Subject: [PATCH] turnip: Set up REG_A6XX_SP_GS_CONFIG Updates GS_CONFIG and HLSQ_GS_CNTL registers to match those emitted by the blob and fd. Part-of: --- src/freedreno/vulkan/tu_pipeline.c | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/src/freedreno/vulkan/tu_pipeline.c b/src/freedreno/vulkan/tu_pipeline.c index fa070fcf957..48f08cb5f3a 100644 --- a/src/freedreno/vulkan/tu_pipeline.c +++ b/src/freedreno/vulkan/tu_pipeline.c @@ -438,19 +438,21 @@ static void tu6_emit_gs_config(struct tu_cs *cs, struct tu_shader *shader, const struct ir3_shader_variant *gs) { - uint32_t sp_gs_config = 0; - if (gs->instrlen) - sp_gs_config |= A6XX_SP_GS_CONFIG_ENABLED; - + bool has_gs = gs->type != MESA_SHADER_NONE; tu_cs_emit_pkt4(cs, REG_A6XX_SP_GS_UNKNOWN_A871, 1); tu_cs_emit(cs, 0); tu_cs_emit_pkt4(cs, REG_A6XX_SP_GS_CONFIG, 2); - tu_cs_emit(cs, sp_gs_config); + tu_cs_emit(cs, COND(has_gs, + A6XX_SP_GS_CONFIG_ENABLED | + A6XX_SP_GS_CONFIG_NIBO(ir3_shader_nibo(gs)) | + A6XX_SP_GS_CONFIG_NTEX(gs->num_samp) | + A6XX_SP_GS_CONFIG_NSAMP(gs->num_samp))); tu_cs_emit(cs, gs->instrlen); tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_GS_CNTL, 1); - tu_cs_emit(cs, A6XX_HLSQ_GS_CNTL_CONSTLEN(align(gs->constlen, 4))); + tu_cs_emit(cs, COND(has_gs, A6XX_HLSQ_GS_CNTL_ENABLED) | + A6XX_HLSQ_GS_CNTL_CONSTLEN(align(gs->constlen, 4))); } static void -- 2.30.2