From 476d96cb5311a4f6e562090cea0b7a444e85a33c Mon Sep 17 00:00:00 2001 From: Nils Asmussen Date: Sat, 21 Mar 2020 10:57:37 +0100 Subject: [PATCH] arch-riscv: make sure only supported modes can be set in SATP. Change-Id: I37c67e491d64bf03d1125e23db28611fa0b16038 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26983 Tested-by: kokoro Reviewed-by: Jason Lowe-Power Maintainer: Jason Lowe-Power --- src/arch/riscv/isa.cc | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/src/arch/riscv/isa.cc b/src/arch/riscv/isa.cc index ca3358e6f..a71733bcb 100644 --- a/src/arch/riscv/isa.cc +++ b/src/arch/riscv/isa.cc @@ -1,6 +1,7 @@ /* * Copyright (c) 2016 RISC-V Foundation * Copyright (c) 2016 The University of Virginia + * Copyright (c) 2020 Barkhausen Institut * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -34,6 +35,7 @@ #include #include "arch/riscv/interrupts.hh" +#include "arch/riscv/pagetable.hh" #include "arch/riscv/registers.hh" #include "base/bitfield.hh" #include "cpu/base.hh" @@ -204,6 +206,18 @@ ISA::setMiscReg(int misc_reg, RegVal val, ThreadContext *tc) ic->setIE(val); } break; + case MISCREG_SATP: + { + // we only support bare and Sv39 mode; setting a different mode + // shall have no effect (see 4.1.12 in priv ISA manual) + SATP cur_val = readMiscRegNoEffect(misc_reg); + SATP new_val = val; + if (new_val.mode != AddrXlateMode::BARE && + new_val.mode != AddrXlateMode::SV39) + new_val.mode = cur_val.mode; + setMiscRegNoEffect(misc_reg, new_val); + } + break; default: setMiscRegNoEffect(misc_reg, val); } -- 2.30.2