From 47835dbedc58dfab1ec1643981f76a478610fa72 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Tue, 26 Jul 2022 16:11:53 +0100 Subject: [PATCH] add example fmvis instruction to trans/svp64.py --- openpower/isatables/RM-2P-1S1D.csv | 1 - src/openpower/sv/trans/svp64.py | 3 ++- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/openpower/isatables/RM-2P-1S1D.csv b/openpower/isatables/RM-2P-1S1D.csv index a505496c..31d93e24 100644 --- a/openpower/isatables/RM-2P-1S1D.csv +++ b/openpower/isatables/RM-2P-1S1D.csv @@ -27,7 +27,6 @@ oris,NORMAL,,2P,EXTRA3,d:RA,s:RS,0,0,RS,0,0,RA,0,0,0 xori,NORMAL,,2P,EXTRA3,d:RA,s:RS,0,0,RS,0,0,RA,0,0,0 xoris,NORMAL,,2P,EXTRA3,d:RA,s:RS,0,0,RS,0,0,RA,0,0,0 subfic,NORMAL,,2P,EXTRA3,d:RT,s:RA,0,0,RA,0,0,RT,0,0,0 -fmvis,NORMAL,,2P,EXTRA3,TODO,0,0,0,FRS,0,0,FRS,0,0,0 cntlzw,NORMAL,,2P,EXTRA3,d:RA;d:CR0,s:RS,0,0,RS,0,0,RA,0,CR0,0 cntlzd,NORMAL,,2P,EXTRA3,d:RA;d:CR0,s:RS,0,0,RS,0,0,RA,0,CR0,0 subfze,NORMAL,,2P,EXTRA3,d:RT;d:CR0,s:RA,0,0,RA,0,0,RT,0,CR0,0 diff --git a/src/openpower/sv/trans/svp64.py b/src/openpower/sv/trans/svp64.py index f669f0d1..86f00a8e 100644 --- a/src/openpower/sv/trans/svp64.py +++ b/src/openpower/sv/trans/svp64.py @@ -1502,7 +1502,8 @@ if __name__ == '__main__': ] lst = [ 'sv.svstep./m=r3 2.v, 4, 0', - 'ternlogi 0,0,0,0x5' + 'ternlogi 0,0,0,0x5', + 'fmvis 5,65535', ] isa = SVP64Asm(lst, macros=macros) log("list", list(isa)) -- 2.30.2