From 4789391217efbc2415b3d75c63d753fc9d6a0ae0 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sun, 8 Apr 2018 13:08:36 +0100 Subject: [PATCH] add on-top-of section --- simple_v_extension.mdwn | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/simple_v_extension.mdwn b/simple_v_extension.mdwn index 4e8059840..9111087d7 100644 --- a/simple_v_extension.mdwn +++ b/simple_v_extension.mdwn @@ -695,6 +695,19 @@ translates effectively to: | URSUB8 rt, ra, rb | Unsigned Halving sub | | +# Impementing V on top of Simple-V + +* Number of Offset CSRs extends from 2 +* Extra register file: vector-file +* Setup of Vector length and bitwidth CSRs now can specify vector-file + as well as integer or float file. +* TODO + +# Implementing P (renamed to DSP) on top of Simple-V + +* Implementors indicate chosen bitwidth support in Vector-bitwidth CSR + (caveat: anything not specified drops through to software-emulation / traps) +* TODO # References -- 2.30.2