From 4792d925fc89020f0ab4052bd007a0b5a426bf13 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Wed, 1 Dec 2021 08:42:37 +0100 Subject: [PATCH] Update CHANGELOG and CODEOWNERS --- CHANGELOG | 21 +++++++++++++++++++++ CODEOWNERS | 1 + 2 files changed, 22 insertions(+) diff --git a/CHANGELOG b/CHANGELOG index 0891e7bcb..851d5dc30 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -5,6 +5,27 @@ List of major changes and improvements between releases Yosys 0.11 .. Yosys 0.11-dev -------------------------- + * Various + - Added iopadmap native support for negative-polarity output enable + - ABC update + + * SystemVerilog + - Support parameters using struct as a wiretype + + * New commands and options + - Added "-genlib" option to "abc" pass + - Added "sta" very crude static timing analysis pass + + * Verific support + - Fixed memory block size in import + + * New back-ends + - Added support for GateMate FPGA from Cologne Chip AG + + * Intel ALM support + - Added preliminary Arria V support + + Yosys 0.10 .. Yosys 0.11 -------------------------- diff --git a/CODEOWNERS b/CODEOWNERS index 26d838bec..19b660dff 100644 --- a/CODEOWNERS +++ b/CODEOWNERS @@ -32,6 +32,7 @@ frontends/ast/ @zachjs techlibs/intel_alm/ @ZirconiumX techlibs/gowin/ @pepijndevos +techlibs/gatemate/ @pu-cc # pyosys misc/*.py @btut -- 2.30.2