From 47aa52ed17d4743909b7e63a59274a13a9361c66 Mon Sep 17 00:00:00 2001 From: Giacomo Travaglini Date: Thu, 17 Sep 2020 16:46:27 +0100 Subject: [PATCH] arch-arm: TLBI ALLE2IS should broadcast to the IS domain This was implemented as a normal ALLE2 hence affecting the current PE only Change-Id: Ib369dd5a4b738daf96a01b5535d7481a97bb3730 Signed-off-by: Giacomo Travaglini Reviewed-by: Nikos Nikoleris Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34795 Tested-by: kokoro --- src/arch/arm/isa.cc | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc index 9ace2367f..cfef0ab07 100644 --- a/src/arch/arm/isa.cc +++ b/src/arch/arm/isa.cc @@ -1711,9 +1711,8 @@ ISA::setMiscReg(int misc_reg, RegVal val) tlbiOp.broadcast(tc); return; } - // AArch64 TLB Invalidate All, EL2, Inner Shareable + // AArch64 TLB Invalidate All, EL2 case MISCREG_TLBI_ALLE2: - case MISCREG_TLBI_ALLE2IS: { assert64(); scr = readMiscReg(MISCREG_SCR); @@ -1722,6 +1721,16 @@ ISA::setMiscReg(int misc_reg, RegVal val) tlbiOp(tc); return; } + // AArch64 TLB Invalidate All, EL2, Inner Shareable + case MISCREG_TLBI_ALLE2IS: + { + assert64(); + scr = readMiscReg(MISCREG_SCR); + + TLBIALL tlbiOp(EL2, haveSecurity && !scr.ns); + tlbiOp.broadcast(tc); + return; + } // AArch64 TLB Invalidate All, EL1 case MISCREG_TLBI_ALLE1: case MISCREG_TLBI_VMALLS12E1: -- 2.30.2