From 47eace0b9f2b9ddd7ae76e06e2ade85ceea88e17 Mon Sep 17 00:00:00 2001 From: Andrew Zonenberg Date: Sat, 7 May 2016 21:29:26 -0700 Subject: [PATCH] Added GP_DELAY cell --- techlibs/greenpak4/cells_sim.v | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/techlibs/greenpak4/cells_sim.v b/techlibs/greenpak4/cells_sim.v index b9cfbe665..be8e66c66 100644 --- a/techlibs/greenpak4/cells_sim.v +++ b/techlibs/greenpak4/cells_sim.v @@ -94,6 +94,35 @@ module GP_COUNT14(input CLK, input wire RST, output reg OUT); endmodule +module GP_DELAY(input IN, output reg OUT); + + parameter DELAY_STEPS = 1; + + //TODO: additional delay/glitch filter mode + + initial OUT = 0; + + generate + + //TODO: These delays are PTV dependent! For now, hard code 3v3 timing + //Change simulation-mode delay depending on global Vdd range (how to specify this?) + always @(*) begin + case(DELAY_STEPS) + 1: #166 OUT = IN; + 2: #318 OUT = IN; + 2: #471 OUT = IN; + 3: #622 OUT = IN; + default: begin + $display("ERROR: GP_DELAY must have DELAY_STEPS in range [1,4]"); + $finish; + end + endcase + end + + endgenerate + +endmodule + module GP_DFF(input D, CLK, output reg Q); parameter [0:0] INIT = 1'bx; initial Q = INIT; -- 2.30.2