From 47ebcd3a40f3bff6c1c577c6cf5fee3fbb84525c Mon Sep 17 00:00:00 2001 From: lkcl Date: Sun, 10 Jan 2021 20:48:58 +0000 Subject: [PATCH] --- openpower/sv/bitmanip.mdwn | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/openpower/sv/bitmanip.mdwn b/openpower/sv/bitmanip.mdwn index ccec185b6..b2d8a926f 100644 --- a/openpower/sv/bitmanip.mdwn +++ b/openpower/sv/bitmanip.mdwn @@ -24,7 +24,7 @@ | RT | RA | RB | unshuf| shuffle | | RT | RA | RB | width | xperm | | RT | RA | RB | type | clmul | -| RT | RA | RB | | | +| RT | RA | RB | type | minmax | | RT | RA | RB | | | | RT | RA | RB | | | | RT | RA | RB | | | @@ -35,7 +35,8 @@ ops | -- | -- | --- | --- | ----- | -- | ------- |--| ---- | | NN | RA | RB | RC | itype | 0 | 0000110 |Rc| bmops | | NN | RA | RB | RC | itype | 1 | 0000110 |Rc| xperm | -| NN | RA | RB | | | | 0100110 |Rc| rsvd | +| NN | RA | RB | RC | itype | 0 | 0100110 |Rc| minmax | +| NN | RA | RB | | | 1 | 0100110 |Rc| rsvd | | NN | RA | RB | sh | itype | SH | 1000110 |Rc| bmopsi | | NN | RA | RB | | | | 1100110 |Rc| rsvd | | NN | RA | RB | RC | itype | 0 | 0001110 |Rc| clmul | @@ -111,6 +112,13 @@ uint_xlen_t bext(uint_xlen_t RA, uint_xlen_t RB) return r; } ``` + +# int min/max + +signed and unsigned min/max for integer. this is sort-of partly synthesiseable in [[sv/svp64]] with pred-result as long as the dest reg is one of the sources, but not both signed and unsigned. when the dest is also one of the srces and the mv fails due to the CR bittest failing this will only overwrite the dest where the src is greater (or less). + +signed/unsigned min/max gives more flexibility. + # ternary bitops Similar to FPGA LUTs: for every bit perform a lookup into a table using an 8bit immediate, or in another register -- 2.30.2