From 47ec4b171f79661b3d3318fb58171280c6d7c0c2 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Tue, 26 May 2020 23:17:18 +0100 Subject: [PATCH] get score6600_multi.py working again --- src/soc/experiment/alu_hier.py | 5 +++++ src/soc/experiment/score6600_multi.py | 6 +++--- src/soc/regfile/regfile.py | 4 ++-- 3 files changed, 10 insertions(+), 5 deletions(-) diff --git a/src/soc/experiment/alu_hier.py b/src/soc/experiment/alu_hier.py index 23c60100..42f38cb4 100644 --- a/src/soc/experiment/alu_hier.py +++ b/src/soc/experiment/alu_hier.py @@ -281,6 +281,11 @@ class BranchOp(Elaboratable): class BranchALU(Elaboratable): def __init__(self, width): + self.p = Dummy() # make look like nmutil pipeline API + self.p.data_i = Dummy() + self.p.data_i.ctx = Dummy() + self.n = Dummy() # make look like nmutil pipeline API + self.n.data_o = Dummy() self.p.valid_i = Signal() self.p.ready_o = Signal() self.n.ready_i = Signal() diff --git a/src/soc/experiment/score6600_multi.py b/src/soc/experiment/score6600_multi.py index 46398bd9..95f12dc3 100644 --- a/src/soc/experiment/score6600_multi.py +++ b/src/soc/experiment/score6600_multi.py @@ -4,7 +4,7 @@ from nmigen.hdl.ast import unsigned from nmigen import Module, Const, Signal, Array, Cat, Elaboratable, Memory from nmigen.back.pysim import Delay -from soc.regfile.regfile import RegFileArray, treereduce +from soc.regfile.regfile import RegFileArray, ortreereduce from soc.scoremulti.fu_fu_matrix import FUFUDepMatrix from soc.scoremulti.fu_reg_matrix import FURegDepMatrix from soc.scoreboard.global_pending import GlobalPending @@ -170,10 +170,10 @@ class CompUnitsBase(Elaboratable): # protected by a single go_wr. multi-issue requires a bus # to be inserted here. if self.units: - data_o = treereduce(self.units, "data_o") + data_o = ortreereduce(self.units, "data_o") comb += self.data_o.eq(data_o) if self.ldstmode: - addr_o = treereduce(self.units, "addr_o") + addr_o = ortreereduce(self.units, "addr_o") comb += self.addr_o.eq(addr_o) for i, alu in enumerate(self.units): diff --git a/src/soc/regfile/regfile.py b/src/soc/regfile/regfile.py index aef0a554..6653fa45 100644 --- a/src/soc/regfile/regfile.py +++ b/src/soc/regfile/regfile.py @@ -84,8 +84,8 @@ class Register(Elaboratable): def ports(self): res = list(self) -def ortreereduce(tree): - return treereduce(tree, operator.or_, lambda x: getattr(x, "data_o")) +def ortreereduce(tree, attr="data_o"): + return treereduce(tree, operator.or_, lambda x: getattr(x, attr)) class RegFileArray(Elaboratable): -- 2.30.2