From 480241bf6d0fcc00389e977cc063a340fd7687e6 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Mon, 1 Jun 2020 19:45:01 +0100 Subject: [PATCH] remove use of reg3 in logical pipeline: CSV files moved RS to position 1 --- libreriscv | 2 +- src/soc/fu/logical/test/test_pipe_caller.py | 7 +------ 2 files changed, 2 insertions(+), 7 deletions(-) diff --git a/libreriscv b/libreriscv index ce306bad..177088bd 160000 --- a/libreriscv +++ b/libreriscv @@ -1 +1 @@ -Subproject commit ce306badc535e08b5fc5e061b26290dce44166ff +Subproject commit 177088bdebe14a2e1173f8302127bbde504c3116 diff --git a/src/soc/fu/logical/test/test_pipe_caller.py b/src/soc/fu/logical/test/test_pipe_caller.py index 04778c63..c8f1ebc2 100644 --- a/src/soc/fu/logical/test/test_pipe_caller.py +++ b/src/soc/fu/logical/test/test_pipe_caller.py @@ -29,13 +29,8 @@ def set_alu_inputs(alu, dec2, sim): # detect the immediate here (with m.If(self.i.ctx.op.imm_data.imm_ok)) # and place it into data_i.b - reg3_ok = yield dec2.e.read_reg3.ok reg1_ok = yield dec2.e.read_reg1.ok - assert reg3_ok != reg1_ok - if reg3_ok: - data1 = yield dec2.e.read_reg3.data - data1 = sim.gpr(data1).value - elif reg1_ok: + if reg1_ok: data1 = yield dec2.e.read_reg1.data data1 = sim.gpr(data1).value else: -- 2.30.2