From 480359bcf644c496c5318e89fe7ad60d95772acd Mon Sep 17 00:00:00 2001 From: Christoph Bumiller Date: Thu, 21 Mar 2013 19:26:01 +0100 Subject: [PATCH] nvc0: enable compression when supported --- src/gallium/drivers/nvc0/nvc0_3d.xml.h | 6 ++++++ src/gallium/drivers/nvc0/nvc0_miptree.c | 5 ++--- src/gallium/drivers/nvc0/nvc0_screen.c | 5 +++++ 3 files changed, 13 insertions(+), 3 deletions(-) diff --git a/src/gallium/drivers/nvc0/nvc0_3d.xml.h b/src/gallium/drivers/nvc0/nvc0_3d.xml.h index 1cf1f96569f..44f96a20f01 100644 --- a/src/gallium/drivers/nvc0/nvc0_3d.xml.h +++ b/src/gallium/drivers/nvc0/nvc0_3d.xml.h @@ -1139,6 +1139,8 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define NVC0_3D_LOGIC_OP_NAND 0x0000150e #define NVC0_3D_LOGIC_OP_SET 0x0000150f +#define NVC0_3D_ZETA_COMP_ENABLE 0x000019cc + #define NVC0_3D_CLEAR_BUFFERS 0x000019d0 #define NVC0_3D_CLEAR_BUFFERS_Z 0x00000001 #define NVC0_3D_CLEAR_BUFFERS_S 0x00000002 @@ -1153,6 +1155,10 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define NVC0_3D_CLIPID_FILL 0x000019d4 +#define NVC0_3D_RT_COMP_ENABLE(i0) (0x000019e0 + 0x4*(i0)) +#define NVC0_3D_RT_COMP_ENABLE__ESIZE 0x00000004 +#define NVC0_3D_RT_COMP_ENABLE__LEN 0x00000008 + #define NVC0_3D_COLOR_MASK(i0) (0x00001a00 + 0x4*(i0)) #define NVC0_3D_COLOR_MASK__ESIZE 0x00000004 #define NVC0_3D_COLOR_MASK__LEN 0x00000008 diff --git a/src/gallium/drivers/nvc0/nvc0_miptree.c b/src/gallium/drivers/nvc0/nvc0_miptree.c index 8c4d7240603..11368043236 100644 --- a/src/gallium/drivers/nvc0/nvc0_miptree.c +++ b/src/gallium/drivers/nvc0/nvc0_miptree.c @@ -41,8 +41,6 @@ nvc0_mt_choose_storage_type(struct nv50_miptree *mt, boolean compressed) uint32_t tile_flags; - compressed = FALSE; /* not yet supported */ - if (unlikely(mt->base.base.bind & PIPE_BIND_CURSOR)) return 0; if (unlikely(mt->base.base.flags & NOUVEAU_RESOURCE_FLAG_LINEAR)) @@ -247,6 +245,7 @@ nvc0_miptree_create(struct pipe_screen *pscreen, struct nouveau_device *dev = nouveau_screen(pscreen)->device; struct nv50_miptree *mt = CALLOC_STRUCT(nv50_miptree); struct pipe_resource *pt = &mt->base.base; + boolean compressed = dev->drm_version >= 0x01000101; int ret; union nouveau_bo_config bo_config; uint32_t bo_flags; @@ -259,7 +258,7 @@ nvc0_miptree_create(struct pipe_screen *pscreen, pipe_reference_init(&pt->reference, 1); pt->screen = pscreen; - bo_config.nvc0.memtype = nvc0_mt_choose_storage_type(mt, TRUE); + bo_config.nvc0.memtype = nvc0_mt_choose_storage_type(mt, compressed); if (!nvc0_miptree_init_ms_mode(mt)) { FREE(mt); diff --git a/src/gallium/drivers/nvc0/nvc0_screen.c b/src/gallium/drivers/nvc0/nvc0_screen.c index b5b4ef10d7a..bf353c48251 100644 --- a/src/gallium/drivers/nvc0/nvc0_screen.c +++ b/src/gallium/drivers/nvc0/nvc0_screen.c @@ -677,6 +677,11 @@ nvc0_screen_create(struct nouveau_device *dev) PUSH_DATA (push, 0x17); } + IMMED_NVC0(push, NVC0_3D(ZETA_COMP_ENABLE), dev->drm_version >= 0x01000101); + BEGIN_NVC0(push, NVC0_3D(RT_COMP_ENABLE(0)), 8); + for (i = 0; i < 8; ++i) + PUSH_DATA(push, dev->drm_version >= 0x01000101); + BEGIN_NVC0(push, NVC0_3D(RT_CONTROL), 1); PUSH_DATA (push, 1); -- 2.30.2